On defect oriented testing for hybrid CMOS/memristor memory

Proceedings of the Asian Test Symposium

Volumn , Issue , 2011, Pages 353-358

  Haron, Nor Zaidi ^a,b   Hamdioui, Said ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b UNIVERSITI TEKNIKAL MALAYSIA MELAKA   (Malaysia)

Author keywords

defect oriented testing; fault models; memory defects; memristor

Indexed keywords

DEFECT ANALYSIS; DEFECT INJECTIONS; DEFECT-ORIENTED TESTING; ELECTRICAL SIMULATION; FABRICATION TECHNIQUE; FAULT MODEL; FAULT MODELS; HYBRID CMOS; HYBRID MEMORIES; MEMORY DEFECTS; MEMORY TECHNOLOGY; MEMRISTOR; NON-VOLATILE; QUALITY IMPROVEMENT; RELIABILITY IMPROVEMENT; SEMICONDUCTOR MEMORY; SIMULATION MODEL; UNDEFINED STATE;

CIRCUIT SIMULATION; COMPUTER SIMULATION; DEFECTS; DESIGN FOR TESTABILITY; RESEARCH; SEMICONDUCTOR STORAGE;

FLASH MEMORY;

EID: 84856139534     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2011.66     Document Type: Conference Paper

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