Redundant residue number system code for fault-tolerant hybrid memories

ACM Journal on Emerging Technologies in Computing Systems

Volumn 7, Issue 1, 2011, Pages

  Haron, Nor Zaidi ^a,b   Hamdioui, Said ^a  

^a Department of Microelectronics   (Netherlands)

^b UNIVERSITI TEKNIKAL MALAYSIA MELAKA   (Malaysia)

Author keywords

Error correction codes; Fault tolerance; Hybrid memories; Nanowire; Residue number system

Indexed keywords

AREA OVERHEAD; DATA STORAGE CAPACITY; DECODING PERFORMANCE; ERROR CORRECTION CAPABILITY; ERROR CORRECTION CODES; FAULT RATES; FAULT-TOLERANT; HYBRID MEMORIES; LOW-POWER CONSUMPTION; MEMORY CELL ARRAYS; PERFORMANCE PENALTIES; REED-SOLOMON; RESIDUE NUMBER SYSTEM; SEMICONDUCTOR MEMORY; TRANSIENT CLUSTERS; TRANSIENT FAULTS;

FAULT TOLERANCE; NANOWIRES; NUMBERING SYSTEMS; PROGRAM PROCESSORS; QUALITY ASSURANCE; SEMICONDUCTOR STORAGE; SIGNAL PROCESSING;

BIT ERROR RATE;

EID: 79951535161     PISSN: 15504832     EISSN: 15504840     Source Type: Journal    
DOI: 10.1145/1899390.1899394     Document Type: Conference Paper

References (34)

1. BARSI, F. AND MAESTRINI, P. 1973. Error correcting properties of redundant residue number systems. IEEE Trans. Comput. 22, 3, 307-315.
2. BISWAS, S., METODI, T. S., CHONG, F. T., AND KASTNER, R. 2007. A pageable, defect-tolerant nanoscale memory system. In Proceedings of IEEE International Symposium on Nanoscale Architecture. 85-92.
3. BULLIS, K. Ultradense molecular memory: Researchers develop a large-scale array of nanoscale memory circuits. http://www.technologyreview.com/nanotech/ 18100/.
4. CALMEC.Molecular electronic technology. http://www.calmec.com/.
5. DEHON, A., GOLDSTEIN, S. C., KUEKES, P., AND LINCOLN, P. 2005. Nonphotolithographic nanoscale memory density prospects. IEEE Trans. Nanotechnol. 4, 2, 215-228. (Pubitemid 40421657)
6. GHOSH, S. AND LINCOLN, P. D. 2008. Dynamic low-density parity check codes for fault-tolerant nanoscale memory. http://www.csl.sri.com/users/shalini/ldpc. pdf.
7. GOH, V. T. AND SIDDIQI, M. U. 2008. Multiple error detection and correction based on redundant residue number systems. IEEE Trans. Comm. 56, 3, 325-330. (Pubitemid 351493751)
8. HARON, N. Z. AND HAMDIOUI, S. 2009. Residue-based code for reliable hybrid memories. In Proceedings of IEEE International Symposium on Nanoscale Architectures. 27-32.
9. HARON, N. Z. AND HAMDIOUI, S. 2011. Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories. In Proceedings of Design, Automation and Test in Europe Conference (DATE). To appear.
10. ITRS. The International Technology Roadmap for Semiconductors. http://www.itrs.net/links/2009itrs/home2009.htm.
11. JEFFERY, C. AND FIGUEIREDO, R. J. O. 2006. Hierarchical fault tolerance for nanoscale memories. IEEE Trans. Nanotechnol. 5, 4, 407-414. (Pubitemid 44102132)
12. KISH, L. B. AND AJAYAN, P. M. 2005. Terrabyte flash memory with carbon nanotubes. Appl. Phys. Lett. 86, 9, 1-2.
13. KÜGELER, C.,MEIER, M., ROSEZIN, R., GILLES, S., AND WASER, R. 2009. High density 3D memory architecture based on the resistive switching effect. J. Solid-State Electron. 53, 12, 1287-1292.
14. LIKHAREV, K. K. 2008. Hybrid CMOS/nanoelectronic circuits: Opportunities and challenges. J. Nanoelectron. Optoelectron. 3, 3, 203-230.
15. LIN, S. AND COSTELLO, D. J. 2004. Error Control Coding: Fundamentals and Applications. Prentice-Hall, Upper Saddle River, NJ.
16. LINCOLN, P. 2009. Challenges in scalable fault tolerance. In Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures. 13-14.
17. LUYKEN, R. J. AND HOFMANN, F. 2003. Concept for hybrid CMOS-molecular non-volatile memories. J. Nanosci. Nanotechnol. 14, 2, 273-276.
18. MATHWORKS. Reed-Solomon decoder simulation. http://www.mathworks.com/ matlabcentral.
19. MISHRA, M. AND GOLDSTEIN, S. C. 2003. Defect tolerance at the end of the roadmap. In Proceedings of International Test Conference. IEEE Computer Society, 1201-1210.
20. NAEIMI, H. AND DEHON, A. 2009. Fault secure encoder and decoder for nanomemory applications. IEEE Trans. VLSI Syst. 17, 4, 473-486.
21. NEUBERGER, G., LIMA, F. D., CARRO, L., AND RIES, R. 2003. A multiple bit upset tolerant SRAM memory. ACM Trans. Design Autom. Electron. Syst. 8, 4, 577-595.
22. ORAILOGLU, A. 2007. Nanoelectronic architectures: Reliable computation on defective devices. In Digest of Workshop on Dependable and Secure Nanocomputing.
23. REED, M. A., CHEN, J., RAWLETT, A. M., PRICE, D. W., AND TOUR, J. M. 2007. Molecular random access memory cell. Appl. Phys. Lett. 78, 23, 3735-3737.
24. RISPAL, L. AND SCHWALKE, U. 2008. Large-scale in situ fabrication of voltage-programmable dual-layer high-kappa dielectric carbon nanotube memory devices with high on/off ratio. IEEE Electron Device Lett. 29, 412, 1349-1352.
25. STRUKOV, D. B. 2006. Digital architectures for hybrid CMOS/nanodevice circuits. Ph.D. thesis, Stony Brook University, NY.
26. STRUKOV, D. B. AND LIKHAREV, K. K. 2004. Prospects for terabit-scale nanoelectronic memories. J. Nanosci. Nanotechnol. 16, 1, 137-148. (Pubitemid 40121546)
27. STRUKOV, D. B. AND LIKHAREV, K. K. 2007. Defect-tolerant architectures for nanoelectronics crossbar memories. J. Nanosci. Nanotechnol. 7, 151-167.
28. SUN, F. AND ZHANG, T. 2007. Defect and transient fault-tolerant system design for hybrid CMOS/nanodevice digital memories. IEEE Trans. Nanotechnol. 6, 3, 341-351.
29. SUN, J. D. AND KRISHNA, H. 1992. A coding theory approach to error control in redundant residue number systems - Part II: Multiple error detection and correction. IEEE Trans. Circuits Syst. 39, 1, 18-34.
30. SZABO, N. AND TANAKA, R. 1967. Residue Arithmetic and its Application to Computer Technology. MC-Graw-Hill, New York.
31. WAISER, R. AND AONO, M. 2007. Nanoionics-based resistive switching memories. Nature Materials 6, 11, 833-840. (Pubitemid 350064191)
32. WANG, W., SWAMY,M. N. S.,AHMAD, M. O., AND WANG, Y. 2003. A study of the residue-to-binary converters for the three-moduli sets. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 50, 2, 235-243.
33. YANG, L.-L. AND HANZO, L. 2001. Redundant residue number system based error correction codes. In Proceedings of the 54th Vehicular Technology Conference. Vol. 3. 1472-1476. (Pubitemid 33088495)
34. ZETTACORE. Zettacore Memory.http://www.zettacore.com/.