-
1
-
-
43549116120
-
Si-nanowire based gate-all-around nonvolatile SONOS memory cell
-
May
-
J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, "Si-nanowire based gate-all-around nonvolatile SONOS memory cell," IEEE Electron Device Lett., vol. 29, no. 5, pp. 518-521, May 2006.
-
(2006)
IEEE Electron Device Lett.
, vol.29
, Issue.5
, pp. 518-521
-
-
Fu, J.1
Singh, N.2
Buddharaju, K.D.3
Teo, S.H.G.4
Shen, C.5
Jiang, Y.6
Zhu, C.X.7
Yu, M.B.8
Lo, G.Q.9
Balasubramanian, N.10
Kwong, D.L.11
Gnani, E.12
Baccarani, G.13
-
2
-
-
4344661847
-
Over-erase phenomenon in SONOS-type Flash memory and its minimization using a hafnium oxide charge storage layer
-
Jul.
-
Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, "Over-erase phenomenon in SONOS-type Flash memory and its minimization using a hafnium oxide charge storage layer," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1143-1147, Jul. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.7
, pp. 1143-1147
-
-
Tan, Y.N.1
Chim, W.K.2
Cho, B.J.3
Choi, W.K.4
-
3
-
-
33645733710
-
Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOStype nonvolatile memory for high-speed operation
-
Apr.
-
Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, and B. J. Cho, "Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOStype nonvolatile memory for high-speed operation," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 654-662, Apr. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.4
, pp. 654-662
-
-
Tan, Y.N.1
Chim, W.K.2
Choi, W.K.3
Joo, M.S.4
Cho, B.J.5
-
4
-
-
79956086917
-
Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells
-
Jun.
-
X. Zhu, Q. Li, D. E. Ioannou, D. Gu, J. E. Bonevich, H. Baumgart, J. S. Suehle, and C. A. Richter, "Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells," Nanotechnology, vol. 22, no. 25, p. 254 020, Jun. 2011.
-
(2011)
Nanotechnology
, vol.22
, Issue.25
, pp. 254
-
-
Zhu, X.1
Li, Q.2
Ioannou, D.E.3
Gu, D.4
Bonevich, J.E.5
Baumgart, H.6
Suehle, J.S.7
Richter, C.A.8
-
5
-
-
40749162001
-
Novel SONOS-type nonvolatile memory device with optimal Al doping in HfAlO charge-trapping layer
-
DOI 10.1109/LED.2007.915380
-
P.-H. Tsai, K.-S. Chang-Liao, C.-Y. Liu, T.-K. Wang, P. J. Tzeng, C. H. Lin, L. S. Lee, and M.-J. Tsai, "Novel SONOS-type nonvolatile memory device with optimal Al doping in HfAlO charge-trapping layer," IEEE Electron Device Lett., vol. 29, no. 3, pp. 265-268, Mar. 2008. (Pubitemid 351386973)
-
(2008)
IEEE Electron Device Letters
, vol.29
, Issue.3
, pp. 265-268
-
-
Tsai, P.-H.1
Chang-Liao, K.-S.2
Liu, C.-Y.3
Wang, T.-K.4
Tzeng, P.J.5
Lin, C.H.6
Lee, L.S.7
Tsai, M.-J.8
-
6
-
-
80052030092
-
Stress effects on self-aligned silicon nanowire junctionless field-effect transistors
-
Sep.
-
C. J. Huang, C. H. Yang, C. Y. Hsueh, J. H. Lee, Y. T. Chang, and S. C. Lee, "Stress effects on self-aligned silicon nanowire junctionless field-effect transistors," IEEE Electron Device Lett., vol. 32, no. 9, pp. 1194-1196, Sep. 2011.
-
(2011)
IEEE Electron Device Lett.
, vol.32
, Issue.9
, pp. 1194-1196
-
-
Huang, C.J.1
Yang, C.H.2
Hsueh, C.Y.3
Lee, J.H.4
Chang, Y.T.5
Lee, S.C.6
-
7
-
-
33745322154
-
Spatial distribution of oxide traps in stressed flash memory
-
DOI 10.1143/JJAP.45.L533
-
B. S. Shim, Y. J. Park, and H. S. Min, "Spatial distribution of oxide traps in stressed Flash memory," Jpn. J. Appl. Phys., vol. 45, no. 21, pp. L533-L535, Jun. 2006. (Pubitemid 43938109)
-
(2006)
Japanese Journal of Applied Physics, Part 2: Letters
, vol.45
, Issue.20-23
-
-
Shim, B.S.1
Park, Y.J.2
Min, H.S.3
-
8
-
-
73349107117
-
Energy and spatial distributions of electron traps throughout SiO2/Al2O3 stacks as the IPD in Flash memory application
-
Jan.
-
X. F. Zheng, W. D. Zhang, B. Govoreanu, D. R. Aguado, J. F. Zhang, and J. Van Houdt, "Energy and spatial distributions of electron traps throughout SiO2/Al2O3 stacks as the IPD in Flash memory application," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 288-296, Jan. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.1
, pp. 288-296
-
-
Zheng, X.F.1
Zhang, W.D.2
Govoreanu, B.3
Aguado, D.R.4
Zhang, J.F.5
Van Houdt, J.6
-
9
-
-
0029725248
-
Mechanisms and characteristics of oxide charge detrapping in n-MOSFETs
-
Jun.
-
T. Wang, T.-E. Chang, L.-P. Chiang, C. Huang, and J. C. Guo, "Mechanisms and characteristics of oxide charge detrapping in n-MOSFETs," in VLSI Symp. Tech. Dig., Jun. 1996, no. 11-13, pp. 232-233.
-
(1996)
VLSI Symp. Tech. Dig.
, Issue.11-13
, pp. 232-233
-
-
Wang, T.1
Chang, T.-E.2
Chiang, L.-P.3
Huang, C.4
Guo, J.C.5
-
10
-
-
36048960747
-
Impact of high-pressure deuterium oxide annealing on the blocking efficiency and interface quality of metal-alumina-nitride-oxide-silicon-type Flash memory devices
-
Nov.
-
M. Chang, M. Hasan, S. Jung, H. Park, M. Jo, H. Choi, and H. Hwang, "Impact of high-pressure deuterium oxide annealing on the blocking efficiency and interface quality of metal-alumina-nitride-oxide-silicon-type Flash memory devices," Appl. Phys. Lett., vol. 91, no. 19, pp. 192111-1-192111-3, Nov. 2007.
-
(2007)
Appl. Phys. Lett.
, vol.91
, Issue.19
, pp. 1921111-1921113
-
-
Chang, M.1
Hasan, M.2
Jung, S.3
Park, H.4
Jo, M.5
Choi, H.6
Hwang, H.7
-
11
-
-
77951190481
-
Wide memory window in graphene oxide charge storage nodes
-
Apr.
-
S. Wang, J. Pu, D. S. H. Chan, B. J. Cho, and K. P. Loh, "Wide memory window in graphene oxide charge storage nodes," Appl. Phys. Lett., vol. 96, no. 14, pp. 143109-1-143109-3, Apr. 2010.
-
(2010)
Appl. Phys. Lett.
, vol.96
, Issue.14
, pp. 1431091-1431093
-
-
Wang, S.1
Pu, J.2
Chan, D.S.H.3
Cho, B.J.4
Loh, K.P.5
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