Stress effects on self-aligned silicon nanowire junctionless field-effect transistors

IEEE Electron Device Letters

Volumn 32, Issue 9, 2011, Pages 1194-1196

  Huang, C J ^a   Yang, C H ^a   Hsueh, C Y ^a   Lee, J H ^a   Chang, Y T ^a   Lee, S C ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Junctionless field effect transistor (JLFET); self aligned process; silicon nanowires (SiNWs); strained silicon

Indexed keywords

APPLIED ELECTRIC FIELD; CURRENT CHANGE; DEVICE FABRICATIONS; HEAVILY DOPED; N TYPE SILICON; OFF CURRENT; ON/OFF RATIO; PINCHOFF; SELF ALIGNED PROCESS; SELF-ALIGNED; SILICON NANOWIRES; SILICON NANOWIRES (SINWS); SOURCE AND DRAINS; STRAINED SILICON; STRESS EFFECTS; STRESS-INDUCED; SUBTHRESHOLD SLOPE; SUBTHRESHOLD SWING;

ELECTRIC FIELDS; ELECTRIC WIRE; ELECTRON MOBILITY; NANOWIRES; TRANSISTORS;

FIELD EFFECT TRANSISTORS;

EID: 80052030092     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2159772     Document Type: Article

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