High-performance and low-voltage challenges for sub-45nm microprocessor circuits

ASICON 2005: 2005 6th International Conference on ASIC, Proceedings

Volumn 1, Issue , 2005, Pages 258-261

  Krishnamurthy, Ram K ^a   Mathew, Sanu K ^a   Anders, Mark A ^a   Hsu, Steven K ^a   Kaul, Himanshu ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; ENERGY DISSIPATION; ENERGY EFFICIENCY; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SWITCHING;

ENERGY-EFFICIENT CIRCUIT; LEAKAGE TOLERANCE; MICROPROCESSOR CIRCUITS; REGISTER FILES;

CMOS INTEGRATED CIRCUITS;

EID: 33847407631     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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