A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop digital DLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Lee, Dong Uk ^a   Lee, Hyun Woo ^a   Kwean, Ki Chang ^a   Choi, Young Kyoung ^a   Moon, Hyong Uk ^a   Kwack, Seung Wook ^a   Kang, Shln Deok ^a   Kim, Kwan Weon ^a   Kim, Yong Ju ^a   Choi, Young Jung ^a   Moran, Patrick ^a   Ahn, Jin Hong ^a   Kih, Joong Sik ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DELAY LINES; ELECTRIC POWER UTILIZATION; VOLTAGE CONTROL;

CAS LATENCY CONTROL; DUAL LOOP CONTROL;

RANDOM ACCESS STORAGE;

EID: 34250793223     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. B. Lee, et al. "A 1.6Gb/s/pin Double-Data-Rate SDRAM with Wave-Pipelined CAS Latency Control," ISSCC Dig. Tech. Papers, pp 210-212, Feb., 2004.
2. H.J. Yoo, "A Study of Pipeline Architectures for High-Speed Synchronous DRAM's," IEEE J. Solid-State Circuits, vol. 32, no. 10, pp. 1597-1603, Oct., 1997.
3. J.T. Kwak, et al. "A Low Cost High Performance Register-Controlled Digital DLL for 1Gbps ×32 DDR SDRAM," Symp. VLSI Circuits, pp. 283-284, Jun., 2003.