A 0.1-to-1.5GHz 4.2mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 282-613

  Yun, Won Joo ^a   Lee, Hyun Woo ^a   Shin, Dongsuk ^a   Kang, Shin Deok ^a   Yang, Ji Yeon ^a   Lee, Hyeng Ouk ^a   Lee, Dong Uk ^a   Sim, Sujeong ^a   Kim, Young Ju ^a   Choi, Won Jun ^a   Song, Keun Soo ^a   Shin, Sang Hoon ^a   Choi, Hyang Hwa ^a   Moon, Hyung Wook ^a   Kwack, Seung Wook ^a   Lee, Jung Woo ^a   Choi, Young Kyoung ^a   Park, Nak Kyu ^a   Kim, Kwan Weon ^a   Choi, Young Jung ^a   Ahn, Jin Hong ^a   Yang, Ye Seok ^a   more..

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; GEAR MANUFACTURE; MICROWAVE CIRCUITS; TIMING CIRCUITS;

ALL DIGITAL; CMOS TECHNOLOGY; DUTY CYCLE CORRECTION; DUTY CYCLE ERROR;

DELAY LOCK LOOPS;

EID: 49549125914     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523167     Document Type: Conference Paper

References (5)

1. J.-T. Kwak, C.-K. Kwon, K.-W. Kim et al., "A Low Cost High Performance Register-Controlled Digital DLL for 1Gbps ×32 DDR SDRAM," Dig. Symp. VLSI Circuits, pp. 283-284, Jun. 2003.
2. D.-U. Lee, H.-W. Lee, K.-C. Kwean et al., "A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL," ISSCC Dig. Tech. Papers, pp. 547-356, Feb. 2006.
3. K. Nakamura, M. Fukaishi, Y. Hirota et al., "A CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending," Dig. Symp. VLSI Circuits, pp. 48-49, Jun. 2000.
4. B. W. Garlepp, et al., "A Portable Digital DLL for High-Speed CMOS Interface Circuits," IEEE J. Solid-State Circuits, vol. 34, no 5, pp. 632-644, May 1999.
5. K.-H. Kim, G.-H. Cho, J.-B. Lee and S.-I. Cho, "Built-in Duty Cycle Corrector Using Coded Phase Blending Scheme for DDR/DDR2 Synchronous DRAM Application," Dig. Symp. VLSI Circuits, pp. 287-288, Jun. 2003.