Critical path selection for delay fault testing based upon a statistical timing model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 11, 2004, Pages 1550-1565

  Wang, Li C ^a,b   Liou, Jing Jia ^a,b   Cheng, Kwang Ting ^a,b  

^a University of California   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Path selection; Process variations; Statistical timing; Testing

Indexed keywords

COMPUTER SIMULATION; MATHEMATICAL MODELS; MECHANICAL TESTING; OPTIMIZATION; PARAMETER ESTIMATION; PROBLEM SOLVING; STATISTICAL METHODS;

DEEP SUBMICRON (DSM); PATH SELECTION; PROCESS VARIATIONS; STATISTICAL TIMING;

CRITICAL PATH ANALYSIS;

EID: 8344278837     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.835137     Document Type: Article

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