Analysis of delay test effectiveness with a multiple-clock scheme

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 407-416

  Liou, Jing Jia ^a   Wang, Li C ^a   Cheng, Kwang Ting ^a   Dworak, Jennifer ^b   Mercer, M Ray ^b   Kapur, Rohit ^c   Williams, Thomas W ^c  

^a University of California   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

DELAY TESTING; MULTIPLE-CLOCK SCHEME; SOFTWARE PACKAGE SPICE; STATISTICAL DELAY EVALUATION;

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; EVALUATION; MATHEMATICAL MODELS; MONTE CARLO METHODS; PROBABILITY; TIMING CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0036443044     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2002.1041786     Document Type: Conference Paper

References (22)

1. Robert C. Aitken, "Nanometer Technology Effects on Fault Models for IC Testing", IEEE Computer, November 1999, pp. 46-51.
2. K-T Cheng, S. Dey, M. Rodgers, and K. Roy, Test Challenges for Deep Sub-Micron Technologies, ACM/IEEE Design Automation Conference 2000.
3. W.-N. Li, S. M. Reddy, and S. K. Sahni, Long and Short Covering Edges in Combinational Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(12):1245-1253. December 1990.
4. S. Tani, M. Teramoto, T. Fukazawa, and K. Matsuhiro. Efficient Path Selection for Delay Testing Based on Partial Path Evaluation. Proceedings of IEEE VLSI Test Symposium, pages 188-193, May 1998.
5. Irith Pomeranz, and Sudhakar M. Reddy, On n-detection test sets and variable n-detection test sets for transition faults, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Volume: 19 Issue: 3, March 2000, pp. 372-383.
6. C. P. Ravikumar, N. Agrawal, and P. Agrawal. Hierarchical Delay Test Generation. Journal of Electronic Testing: Theory and Applications, 10(3): 188-193, June 1997.
7. K. Antreich, A. Ganz, and P. Tafertshofer, Statistical Analysis of Delay Faults-Theory and Efficient Computation. AEU-International Journal of Electronics and Communications, 51(3): 117-130. May 1997.
8. K. Baker, G. Gronthoud, M. Lousberg, I. Schanstra and C. Hawkins, Defect-Based Delay Testing of Resistive Vias-Contacts, A Critical Evaluation. Proceedings of IEEE International Test Conference, pages 467-476. September 1999.
9. M. A. Breuer, C. Gleason, and S. Gupta, New Validation and Test Problems for High Performance Deep Sub-Micron VLSI Circuits. Tutorial Notes, IEEE VLSI Test Symposium, April 1997.
10. A. Krstić and K.-T. Cheng. Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers, Boston, MA, 1998.
11. J.-J. Liou, K.-T. Cheng, and D. Mukherjee. Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. Proceedings of IEEE VLSI Test Symposium, pages 97-104, April 2000.
12. J.-J. Liou, A. Krstić, K.-T. Cheng, D. Mukherjee, and S. Kundu, Performance Sensitivity Analysis Using Statistical Methods and Its Applications to Delay Testing. Proceedings of Asian South Pacific Design Automation Conference, pages 587-592, January 2000.
13. J.-J. Liou, A. Krstić, Li-C. Wang, and K.-T. Cheng. False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation. in Proceedings of Design Automation Conference, June 2002.
14. J-J. Liou, L-C. Wang, K-T. Cheng, J. Dworak, M. R. Mercer, R. Kapur, and T.W. Williams. Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes. in Proceedings of Design Automation Coneference, June 2002.
15. W. W. Mao and M. D. Ciletti. A Variable Observation Time Method for Testing Delay Faults. Proceedings of Design Automation Conference, pages 728-731, June 1990.
16. V. S. Iyengar and G. Vijayan, Optimized Test Application Timing for AC Test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(11):1439-1449, November 1992.
17. D. Dumas, P. Girard, C. Landrault, and S. Pravossoudovitch, Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. Proceedings of European Design and Test Conference, pages 518-523, 1994.
18. W. B. Jone and Y. P. Ho. Delay Fault Coverage Enhancement Using Variable Observation Times. Journal of Electronic Testing: Theory and Applications, 11(2):131-146, October 1997.
19. Anacad. Eldo v4.4x User's Manual. 1996.
20. N. N. Tendolkar, Analysis of Timing Failures Due to Random AC defects in VLSI modules. Proceedings of Design Automation Conference, pages 709-714, June 1985.
21. J. P. de Gyvez. Integrated Circuits Defect-Sensitivity: Theory and Computational Models. Kluwer Academic Publishers, Boston, MA, 1993.
22. Synopsys. Design Compiler Reference Manual. May 2000.