Hierarchical Delay Test Generation

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 10, Issue 3, 1997, Pages 231-244

  Ravikumar, C P ^a,d,e,f   Agrawal, Nitin ^a,b   Agarwal, Parul ^a,c,g,h  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^b Prestige Meredian ^*  (India)

^c The Department of Civil and Environmental Engineering   (United States)

^d University of Southern California   (United States)

^e INDIAN INSTITUTE OF SCIENCE   (India)

^f BANGALORE UNIVERSITY   (India)

^g UNIVERSITY OF MICHIGAN   (United States)

^h UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

Delay test generation; Hierarchical testing; Path selection

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMBINATORIAL CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SOFTWARE; DIGITAL CIRCUITS; ERROR DETECTION; FAILURE ANALYSIS;

DELAY TESTING; SOFTWARE PACKAGE MODET; TIMING ERRORS;

ELECTRONIC EQUIPMENT TESTING;

EID: 0031163978     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008267608838     Document Type: Article

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