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1
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34548841783
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A 14 b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz signal bandwidth and 12 b ENOB
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Feb
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G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A. Melodia, and V. Melini, "A 14 b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz signal bandwidth and 12 b ENOB," Digest of Technical Papers. ISSCC 2006., pp. 131-140, Feb 2006.
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(2006)
Digest of Technical Papers. ISSCC 2006
, pp. 131-140
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Mitteregger, G.1
Ebner, C.2
Mechnig, S.3
Blon, T.4
Holuigue, C.5
Romani, E.6
Melodia, A.7
Melini, V.8
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3
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49549112502
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A 100mW 10MHz BW CT Sigma-Delta modulator with 87dB DR and 91dBc IMD
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Feb
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W. Yang, W. Schofield, H. Shibata, S. Korrapati, A. Shaikh, N. Abaskharoun, and D. Ribner, "A 100mW 10MHz BW CT Sigma-Delta modulator with 87dB DR and 91dBc IMD," Digest of Technical Papers. ISSCC 2008., pp. 498-631, Feb 2008.
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(2008)
Digest of Technical Papers. ISSCC 2008
, pp. 498-631
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Yang, W.1
Schofield, W.2
Shibata, H.3
Korrapati, S.4
Shaikh, A.5
Abaskharoun, N.6
Ribner, D.7
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4
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77954166795
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Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique
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July
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S. Pavan and P. Sankar, "Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique," IEEE Journal of Solid-State Circuits., vol. 45, no. 7, pp. 1365-1379, July 2010.
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(2010)
IEEE Journal of Solid-State Circuits
, vol.45
, Issue.7
, pp. 1365-1379
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Pavan, S.1
Sankar, P.2
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5
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79551512092
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Alias rejection of continuous-time ΔΣ modulators with switched-capacitor feedback DACs
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S. Pavan, "Alias rejection of continuous-time ΔΣ modulators with switched-capacitor feedback DACs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 2, pp. 1-10.
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IEEE Transactions on Circuits and Systems I: Regular Papers
, vol.58
, Issue.2
, pp. 1-10
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Pavan, S.1
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6
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77950231797
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Systematic design centering of continuous time oversampling converters
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-, "Systematic design centering of continuous time oversampling converters,"IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 3, pp. 158-162, 2010.
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(2010)
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol.57
, Issue.3
, pp. 158-162
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Pavan, S.1
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7
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54249147523
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A 56mW continuous-time quadrature cascaded ΣΔ modulator with 77 dB DR in a near zero-IF 20MHz band
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Dec
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L. Breems, R. Rutten, R. van Veldhoven, and G. van der Weide, "A 56mW continuous-time quadrature cascaded ΣΔ modulator with 77 dB DR in a near zero-IF 20MHz band," IEEE Journal of Solid-State Circuits., vol. 42, no. 12, pp. 2696-2705, Dec 2007.
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(2007)
IEEE Journal of Solid-State Circuits.
, vol.42
, Issue.12
, pp. 2696-2705
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Breems, L.1
Rutten, R.2
Van Veldhoven, R.3
Van Der Weide, G.4
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8
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41549118015
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A 12-bit, 10-MHz bandwidth, continuous-time ΣΔ ADC with a 5-bit, 950-MS/s VCO-based quantizer
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DOI 10.1109/JSSC.2008.917500
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M. Straayer and M. Perrott, "A 12 b,10MHz bandwidth continuous-time ΣΔ ADC with a 5b 950 Ms/s VCO-Based quantizer," IEEE Journal of Solid-State Circuits., vol. 43, no. 4, pp. 805-814, Apr 2008. (Pubitemid 351464073)
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(2008)
IEEE Journal of Solid-State Circuits
, vol.43
, Issue.4
, pp. 805-814
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Straayer, M.Z.1
Perrott, M.H.2
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9
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70349283738
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A 0.13 μm CMOS 78 dB SNDR 87mW 20 MHz BW CT Sigma Delta ADC with VCO-based integrator and quantizer
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Feb
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M. Park and M. Perrott, "A 0.13 μm CMOS 78 dB SNDR 87mW 20 MHz BW CT Sigma Delta ADC with VCO-based integrator and quantizer," Digest of Technical Papers, ISSCC 2009., pp. 170-171,171a, Feb 2009.
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(2009)
Digest of Technical Papers, ISSCC 2009
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Park, M.1
Perrott, M.2
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10
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70349271262
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A 20MHz BW 68 dB DR CT Sigma Delta ADC based on a multi-bit time-domain quantizer and feedback element
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Feb
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V. Dhanasekaran, M. Gambhir, M. Elsayed, E. Sanchez-Sinencio, J. Silva-Martinez, C. Mishra, L. Chen, and E. Pankratz, "A 20MHz BW 68 dB DR CT Sigma Delta ADC based on a multi-bit time-domain quantizer and feedback element," Digest of Technical Papers. ISSCC 2009., pp. 174-175,175a, Feb 2009.
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(2009)
Digest of Technical Papers. ISSCC 2009
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Dhanasekaran, V.1
Gambhir, M.2
Elsayed, M.3
Sanchez-Sinencio, E.4
Silva-Martinez, J.5
Mishra, C.6
Chen, L.7
Pankratz, E.8
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11
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72849146020
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A single bit 6.8mW 10MHz power-optimized continuous-time Sigma-Delta with 67 dB DR in 90 nm CMOS
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Sep
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P. Crombez, G. Van der Plas, M. Steyaert, and J. Craninckx, "A single bit 6.8mW 10MHz power-optimized continuous-time Sigma-Delta with 67 dB DR in 90 nm CMOS," Proceedings of the European Solid-State Circuits Conference, 2009, pp. 336-339, Sep 2009.
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(2009)
Proceedings of the European Solid-State Circuits Conference, 2009
, pp. 336-339
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Crombez, P.1
Van Der Plas, G.2
Steyaert, M.3
Craninckx, J.4
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12
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49549121624
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A 28mW spectrum-sensing reconfigurable 20MHz 72 dB SNR 70 dB SNDR DT Sigma Delta ADC for 802.11n/WiMAX Receivers
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Feb
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P. Malla, H. Lakdawala, K. Kornegay, and K. Soumyanath, "A 28mW spectrum-sensing reconfigurable 20MHz 72 dB SNR 70 dB SNDR DT Sigma Delta ADC for 802.11n/WiMAX Receivers," Digest of Technical Papers. ISSCC 2008., pp. 496-631, Feb 2008.
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(2008)
Digest of Technical Papers. ISSCC 2008
, pp. 496-631
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Malla, P.1
Lakdawala, H.2
Kornegay, K.3
Soumyanath, K.4
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13
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77950207345
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A fifth-order continuous-time Delta-Sigma modulator with single-opamp resonator
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Apr
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K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho, and A. Matsuzawa, "A fifth-order continuous-time Delta-Sigma modulator with single-opamp resonator," IEEE Journal of Solid-State Circuits., vol. 45, no. 4, pp. 697-706, Apr 2010.
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(2010)
IEEE Journal of Solid-State Circuits
, vol.45
, Issue.4
, pp. 697-706
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Matsukawa, K.1
Mitani, Y.2
Takayama, M.3
Obata, K.4
Dosho, S.5
Matsuzawa, A.6
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