High-performance ge mos capacitors by o2 plasma passivation and o2 ambient annealing

IEEE Electron Device Letters

Volumn 32, Issue 12, 2011, Pages 1656-1658

  Xie, Qi ^a   Deng, Shaoren ^a   Schaekers, Marc ^b   Lin, Dennis ^b   Caymax, Matty ^b   Delabie, Annelies ^b   Jiang, Yulong ^c   Qu, Xinping ^c   Deduytsche, Davy ^a   Detavernier, Christophe ^a  

^a GHENT UNIVERSITY   (Belgium)

^b IMEC   (Belgium)

^c FUDAN UNIVERSITY   (China)

Author keywords

Ge; Interface passivation; O2 ambient annealing

Indexed keywords

C-V HYSTERESIS; CAPACITANCE VOLTAGE; CMOS DEVICES; COMPREHENSIVE PROPERTIES; ENERGY DISTRIBUTIONS; EQUIVALENT OXIDE THICKNESS; FLAT BAND; GATE LEAKAGE CURRENT DENSITY; GATE STACKS; HIGH QUALITY; IN-SITU; INTERFACE PASSIVATION; MODULATION EFFICIENCY; N-TYPE GE; PLASMA PASSIVATION; POSITIVE BIAS; STRONG INVERSION;

ANNEALING; CMOS INTEGRATED CIRCUITS; GERMANIUM; GERMANIUM OXIDES; HAFNIUM OXIDES; LEAKAGE CURRENTS; PASSIVATION; PLASMAS;

MOS CAPACITORS;

EID: 81855194369     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2166993     Document Type: Article

References (15)

1. M. Caymax, G. Eneman, F. Bellenger, C. Merckling, A. Delabie, G.Wang, R. Loo, E. Simoen, J. Mitard, B. Jaeger, G. Hellings, K. Meyer, and M. Heyns, "Germanium for advanced CMOS anno 2009: A SWOT analysis," in IEDM Tech. Dig., 2009, pp. 461-464.
2. A. Delabie, F. Bellenger, M. Houssa, T. Conard, S. V. Elshocht, M. Caymax,M. Heyns, and M. Meuris, "Effective electrical passivation of Ge(100) for high-k gate dielectric layers using germanium oxide," Appl. Phys. Lett., vol. 91, no. 8, p. 082904, Aug. 2007.
3. 2-based technology," IEEE Electron Device Lett., vol. 31, no. 5, pp. 402-404, May 2010.
4. 2 n-MOSFETs with two-step oxidation," IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1295-1301, May 2011.
5. 2 surface passivation," Appl. Phys. Lett., vol. 93, no. 3, p. 032104, Jul. 2008.
6. 2 surface passivation," Appl. Phys. Lett., vol. 93, no. 7, p. 073504, Aug. 2008.
7. C. Henkel, O. Bethge, S. Abermann, S. Puchner, H. Hutter, and E. Bertagnolli, "Pt-assisted oxidation of (100)-Ge/High-k interfaces and improvement of their electrical quality," Appl. Phys. Lett., vol. 97, no. 15, p. 152 904, Oct. 2010.
8. D. Kuzum, T. Krishnamohan, A. J. Pethe, A. K. Okyay, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, "Ge-interface engineering with ozone oxidation for low interface-state density," IEEE Electron Device Lett., vol. 29, no. 4, pp. 328-330, Apr. 2008.
9. 2 interlayer for high-k gate dielectrics/Ge by electron-cyclotron-resonance plasma techniques," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 282-287, Jan. 2010.
10. 2 plasma," Electrochem. Solid-State Lett., vol. 14, no. 5, pp. G20-G22, Feb. 2011.
11. R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, "Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation," Appl. Phys. Lett., vol. 98, no. 11, p. 112 902, Mar. 2011.
12. D. Lin, G. Brammertz, S. Sioncke, C. Fleischmann, A. Delabie, K. Martens, H. Bender, T. Conard, W. H. Tseng, J. C. Lin, W. E. Wang, K. Temst, A. Vatomme, J. Mitard, M. Caymax, M. Meuris, M. Heyns, and T. Hoffmann, "Enabling the high performance InGaAs/Ge CMOS: A common gate stack solution," in IEDM Tech. Dig., 2009, pp. 327-330.
13. E. J. Kim, L. Wang, P. M. Asbeck, K. C. Saraswat, and P. C. McIntyre, "Border traps in Al2O3/In0.53Ga0.47As(100) gate stacks and their passivation by hydrogen anneals," Appl. Phys. Lett., vol. 96, no. 1, p. 012906, Jan. 2010.
14. G. Brammertz, K. Martens, S. Sioncke, A. Delabie, and M. Caymax, "Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures," Appl. Phys. Lett., vol. 91, no. 13, p. 133 510, Sep. 2007.
15. K. Marten, C. O. Chui, G. Brammertz, B. D. Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes, and G. Groeseneken, "On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 547-556, Feb. 2008.