A multiple-valued logic with merged single-electron and MOS transistors

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 147-150

  Inokawa, Hiroshi ^a   Fujiwara, Akira ^a   Takahashi, Yasuo ^a  

^a Kashino Diverse Brain Research Laboratory of NTT Communication Science Laboratories   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CURRENT VOLTAGE CHARACTERISTICS; ENERGY GAP; FREQUENCY CONVERTERS; GATES (TRANSISTOR); LOGIC CIRCUITS; OXIDATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE;

MULTIPLE-VALUED ADDER; MULTIPLE-VALUED LOGIC; SINGLE-ELECTRON TRANSISTORS;

MOSFET DEVICES;

EID: 0035718150     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations
2. Beyond-binary circuits for signal processing
3. Heterojunction bipolar technology for emitter-coupled multiple-valued logic in gigahertz adders and multipliers
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5. Complementary digital logic based on the Coulomb blockade
6. The single-electron transistor
7. Multiple-valued inverter using a single-electron-tunneling circuit
8. Single-electron multiple-valued base-n full adder circuit using a bunch of electrons as a unit logic value
9. Size dependence of the characteristics of Si single-electron transistors on SIMOX substrates
10. Mechanism of potential profile formation in silicon single-electron transistors fabricated using pattern-dependent oxidation
11. Asynchronous analogue-to-digital converter for single-electron circuits
12. Single-electron flash analog-to-digital converter