Accurate modeling of quantum-dot based multi tunnel junction memory: Optimization and process dispersions analyzes for DRAM applications

European Solid-State Device Research Conference

Volumn , Issue , 2002, Pages 403-406

  Le Royer, Cyrille ^a   Le Carval, Gilles ^a   Fraboulet, David ^a   Sanquer, Marc ^b  

^a CEA LETI   (France)

^b CEA/DSM DRFMC/SPSMS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DISPERSIONS; DYNAMIC RANDOM ACCESS STORAGE; QUANTUM CHEMISTRY; SEMICONDUCTOR QUANTUM DOTS; TUNNEL JUNCTIONS;

ACCURATE MODELING; ELECTRON TRANSPORT; PROCESS CONDITION; PROCESS DISPERSION; QUANTUM LEVELS; RETENTION CHARACTERISTICS; ROOM TEMPERATURE; TECHNOLOGICAL PARAMETERS;

MAGNETIC DEVICES;

EID: 8144220925     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194953     Document Type: Conference Paper

References (7)

1. L. Palun and J. Gautier, "The Multi-Tunnel Junction Single Electron Memory: Architecture and Simulation", SSDM, Tokyo, 1999, pp. 88-89.
2. K. K. Likharev, "Single-Electron Devices and Their Applications", Proceedings of the IEEE, Vol. 87, Issue 4, April 1999, pp. 606-632.
3. C. Le Royer, et al, "Modeling and Simulation of Single-Electron Multi Tunnel Junction Memory: Architecture and Simulation", MSM, April 2002, San Juan (to be published).
4. H. Grabert, et al, Single Charge Tunneling : Coulomb Blockade Phenomena in Nanostructures, Series B: Physics Vol 294, NATO ASI Series, Plenum Press, 1992.
5. S. Putot, et al, "A Fast and Accurate Computation of Interconnect Capacitance", IEDM Technical Digest. International, 1999, pp. 893-897.
6. L. F. Register, et al, "Analytic model for direct tunneling in polycrystalline silicon-gate metal-oxydesemiconductor devices", Applied Physics Letters, Vol. 74, No 3, 18 January 1999, pp. 457-459.
7. SmartSpice/UTMOST III, Modeling Manual, Silvaco International, September 1999, pp. 3.37-3.38