Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors

Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11

Volumn , Issue , 2011, Pages 365-374

  Ahmed, Waheed ^a   Shafique, Muhammad ^a   Bauer, Lars ^a   Henkel, Jörg ^a  

^a KARLSRUHE INSTITUTE OF TECHNOLOGY   (Germany)

Author keywords

Instruction set extensions; Multi grained reconfigurable architectures; Reconfigurable computing; Run time systems

Indexed keywords

ADAPTIVE RESOURCE MANAGEMENT; FUNCTIONAL BLOCK; INSTRUCTION SET EXTENSION; MULTI CORE; MULTI-CORE PROCESSOR; PERFORMANCE CONSTRAINTS; RE-CONFIGURABLE; RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE COMPUTING; RECONFIGURABLE FABRICS; RECONFIGURABLE PROCESSORS; RUNTIME MANAGEMENT; RUNTIME SYSTEMS; RUNTIMES;

BENCHMARKING; CODES (SYMBOLS); CRITICALITY (NUCLEAR FISSION); EMBEDDED SYSTEMS; MANAGEMENT; MULTITASKING; QUALITY OF SERVICE; VIDEO CONFERENCING;

RECONFIGURABLE HARDWARE;

EID: 81355132226     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2039370.2039426     Document Type: Conference Paper

References (27)

1. R. Koenig et al., "KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture", DATE, pp. 819-824, 2010.
2. D. Göhringer et al., "Runtime adaptive multi-processor system- on-chip: RAMPSoC", IPDPS, pp. 1-7, 2008.
3. M. A. Watkins et al., "Shared Reconfigurable Architectures for CMPs", FPL, pp. 299-304, 2008.
4. http://www.xilinx.com/.
5. Q. Cai et al., "Meeting Points: Using Thread Criticality to Adapt Multicore Hardware to Parallel Regions", PACT, pp. 240-249, 2008.
6. A. Bhattacharjee et al., "Thread Criticality Predictors for Dynamic Performance Power, and Resource Management in Chip Multiprocessors", ISCA, pp. 290-301, 2009.
7. K. Bazargan et al., "Fast template placement for reconfigurable computing systems", IEEE Design and Test of Computers, pp. 68-83, 2000.
8. G. Chen et al., "Configuration-sensitive process scheduling for FPGA-based computing platforms", DATE, pp. 486-493, 2004.
9. O. Diessel et al., "Dynamic scheduling of tasks on partially reconfigurable FPGAs", IEEE Proceedings - Computers and Digital Techniques, pp. 181-188, 2000.
10. C. Steiger et al., "Operating systems for reconfigurable embedded platforms: Online scheduling of real time tasks", IEEE Transactions on Computers, pp.1392-1407, 2004.
11. E. El-Araby el al., "Virtualizing and sharing reconfigurable resources in High-Performance Reconfigurable Computing systems", HPRCTA, pp. 1-8, 2008.
12. A. Gavrilovska et al., "High-Performance Hypervisor Architectures: Virtualization in HPC Systems", HPCVirt, 2007.
13. G. Smit et al., "Overview of the 4s project", International Symposium on System-on-Chip, pp. 70-73, 2005.
14. N. Voros et al., "Dynamic System Reconfiguration in Heterogeneous Platforms - The MORPHEUS Approach", Lecture Notes in Electrical Engineering, Vol. 40, Springer 2009.
15. P. G. Zaykov et al., "Reconfigurable multi-threading architectures: A survey", SAMOS, pp. 263-274, 2009.
16. Enno Lübbers and Marco Platzner, "ReconOS: An RTOS supporting hard- and software threads", FPL, pp.441-446, 2007.
17. K. Wu et al., "MT-ADRES: Multithreading on Coarse- Grained Reconfigurable Architecture", International Journal of Electronics, Volume 95, Issue 7, pp. 761-776, 2008.
18. W. Ahmed et al., "mRTS: Run-Time System for Reconfigurable Processors with Multi-Grained Instruction-Set Extensions", DATE, pp. 1554-1559, 2011.
19. C. Haung and F. Vahid, "Dynamic Coprocessor Management for FPGA-Enhanced Compute Platforms", Int. Conf. on Compiler, Architectures, and Synth. for Embedded Systems, pp. 71-78, 2008.
20. V. Gupta et al., "Self-adaptive admission control policies for resource-sharing systems", in SIGMETRICS, pp. 311-322, 2009.
21. C. Dumitrescu, I. Foster, "Usage policy-based CPU sharing in virtual organizations", GRID, pp. 53-60, 2004.
22. L. Bauer et al., "Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set", DATE, pp. 752-757, 2008.
23. T. Mitra et al., "An efficient framework for dynamic reconfiguration of instruction-set customization", CASES, pp. 135-144, 2007.
24. L. Pozzi et al., "Introduction of Local Memory Elements in Instruction Set Extensions", DAC, pp. 729-734, 2004.
25. A. Galstyan et al., "Resource Allocation Games With Changing Resource Capacities", AAMAS, pp. 145-152, 2003.
26. K-M. Lam, H-F. Leung, "An Adaptive Strategy for Resource Allocation Modeled as Minority Game", in SASO, pp. 193- 204, 2007.
27. C. Dumitrescu, I. Foster, "Usage policy-based CPU sharing in virtual organizations", GRID, pp. 53-60, 2004.