-
1
-
-
70350380178
-
Runtime Adaptive Extensible Embedded Processors - A Survey
-
H. P. Huynh, T. Mitra, "Runtime Adaptive Extensible Embedded Processors - A Survey", In Int'l Conf. on Embedded computer Systems, Architectures, Modeling and Simulation (SAMOS), pp. 215-225, 2009.
-
(2009)
Int'l Conf. on Embedded Computer Systems, Architectures, Modeling and Simulation (SAMOS)
, pp. 215-225
-
-
Huynh, H.P.1
Mitra, T.2
-
3
-
-
33746868352
-
Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes
-
F-J. Veredas et al., "Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes", In Int'l Conf. on Field Programmable Logic and Applications (FPL), pp. 106-111, 2005.
-
(2005)
Int'l Conf. on Field Programmable Logic and Applications (FPL)
, pp. 106-111
-
-
Veredas, F.-J.1
-
4
-
-
79957553482
-
-
PACT XPP Technologies, "Programming XPP-III Processors", http://www.pactxpp.com/main/download/XPP-III-programming-WP.
-
Programming XPP-III Processors
-
-
-
5
-
-
77953118548
-
KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture
-
R. Koenig et al., "KAHRISMA: A Novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array Architecture", In Int'l Conf. on Design, Automation, and Test in Europe (DATE), pp.819-824, 2010.
-
(2010)
Int'l Conf. on Design, Automation, and Test in Europe (DATE)
, pp. 819-824
-
-
Koenig, R.1
-
6
-
-
49749147472
-
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
-
L. Bauer et al., "Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set", In Int'l Conf. on Design, Automation, and Test in Europe (DATE), pp.752-757, 2008.
-
(2008)
Int'l Conf. on Design, Automation, and Test in Europe (DATE)
, pp. 752-757
-
-
Bauer, L.1
-
9
-
-
21244483518
-
Lessons learned from designing the MONTIUM - A coarsegrained reconfigurable processing tile
-
G. Samit et al., "Lessons learned from designing the MONTIUM - a coarsegrained reconfigurable processing tile", In Int'l Symp. on System-on-Chip (SoC), pp. 29-32, 2004.
-
(2004)
Int'l Symp. on System-on-Chip (SoC)
, pp. 29-32
-
-
Samit, G.1
-
10
-
-
34547431523
-
Reconfigurable hardware and software architectural constructs for the enablement of resilient computing systems
-
P. Master, "Reconfigurable hardware and software architectural constructs for the enablement of resilient computing systems", In Int'l Conf. on Application specific Systems, Architectures and Processors (ASAP), pp. 50-55, 2006.
-
(2006)
Int'l Conf. on Application Specific Systems, Architectures and Processors (ASAP)
, pp. 50-55
-
-
Master, P.1
-
11
-
-
63349102619
-
Dynamic Coprocessor Management for FPGA-Enhanced Compute Platforms
-
C. Huang et al., "Dynamic Coprocessor Management for FPGA-Enhanced Compute Platforms", Int'l Conf. on Compilers, Architectures, and Synthesis for Embedded System (CASES), pp.71-78, 2008.
-
(2008)
Int'l Conf. on Compilers, Architectures, and Synthesis for Embedded System (CASES)
, pp. 71-78
-
-
Huang, C.1
-
13
-
-
8744241430
-
The MOLEN polymorphic processor
-
S. Vassiliadis et al., "The MOLEN polymorphic processor", in IEEE Transactions on Computers (TC), vol. 53, no. 11, pp. 1363-1375, 2004.
-
(2004)
IEEE Transactions on Computers (TC)
, vol.53
, Issue.11
, pp. 1363-1375
-
-
Vassiliadis, S.1
-
14
-
-
79957568818
-
-
http://www.xilinx.com/products/v4q/lx.htm
-
-
-
-
15
-
-
0033703884
-
CHIMAERA: A high performance architecture with a tightlycoupled reconfigurable functional unit
-
Z. Ye et al., "CHIMAERA: a high performance architecture with a tightlycoupled reconfigurable functional unit", Int'l Symp. On Computer Architecture (ISCA), pp. 225-235, 2000.
-
(2000)
Int'l Symp. On Computer Architecture (ISCA)
, pp. 225-235
-
-
Ye, Z.1
-
16
-
-
0242551725
-
A VLIW processor with reconfigurable instruction set for embedded applications
-
A. Lodi et al., "A VLIW processor with reconfigurable instruction set for embedded applications", Journal of Solid-State Circuits, 38(11): pp.1876-1886, 2003.
-
(2003)
Journal of Solid-State Circuits
, vol.38
, Issue.11
, pp. 1876-1886
-
-
Lodi, A.1
-
17
-
-
77954563702
-
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms
-
M. Shafique et al., "Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms", In Journal of Signal Processing Systems (JSPS), pp.183-210, 2010.
-
(2010)
Journal of Signal Processing Systems (JSPS)
, pp. 183-210
-
-
Shafique, M.1
-
18
-
-
38849103565
-
An efficient framework for dynamic reconfiguration of instruction-set customization
-
T. Mitra et al., "An efficient framework for dynamic reconfiguration of instruction-set customization", Int'l Conf. on Compilers, Architectures, and Synthesis for Embedded System (CASES), pp.135-144, 2007.
-
(2007)
Int'l Conf. on Compilers, Architectures, and Synthesis for Embedded System (CASES)
, pp. 135-144
-
-
Mitra, T.1
-
19
-
-
4444275354
-
Introduction of Local Memory Elements in Instruction Set Extensions
-
L. Pozzi et al, "Introduction of Local Memory Elements in Instruction Set Extensions", In Design Automation Conference (DAC), pp.729-734, 2004.
-
(2004)
Design Automation Conference (DAC)
, pp. 729-734
-
-
Pozzi, L.1
|