An efficient framework for dynamic reconfiguration of instruction-set customization

CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2007, Pages 135-144

  Huynh, Huynh Phung ^a   Sim, Joon Edward ^a   Mitra, Tulika ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Customizable processors; Dynamic reconfiguration; Instruction set extensions; Temporal partitioning

Indexed keywords

ALGORITHMS; ITERATIVE METHODS; PROBLEM SOLVING; PROGRAM PROCESSORS;

CUSTOMIZABLE PROCESSORS; DYNAMIC RECONFIGURATION; INSTRUCTION-SET EXTENSIONS; TEMPORAL PARTITIONING;

DYNAMIC PROGRAMMING;

EID: 38849103565     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289881.1289906     Document Type: Conference Paper

References (28)

1. OpenIMPACT Compiler. http://www.gelato.uiuc.edu/.
2. ARC International. Customizing a soft microprocessor core.
3. J. M. Arnold. S5: The architecture and development flow of a software configurable processor. In FPT, 2005.
4. M. Arnold and H. Corporaal. Designing domain-specific processors. In CODES, 2001.
5. K. Atasu, L. Pozzi, and P. Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints. In DAC, 2003.
6. S. Banerjee, E. Bozorgzadeh, and N. Dutt. Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. In DAC, 2005.
7. K. Bondalapati and V. K. Prasanna. Mapping loops onto reconfigurable architectures. In FPL, 1998.
8. K. S. Chatha and R. Vemuri. Hardware-software codesign for dynamically reconfigurable architectures. In FPL, 1999.
9. N. Cheung, S. Parameswaran, and J. Henkel. Inside: Instruction selection/identification & design exploration for extensible processors. In ICCAD, 2002.
10. N. Clark, H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customization. In MICRO, 2003.
11. J. Cong et al. Application-specific instruction generation for configurable processor architectures. In FPGA, 2004.
12. N. G. de Bruijin. Asymptotic Methods in Analysis. Dover Publications, 1981.
13. P. Faraboschi et al. Lx: A technology platform for customizable VLIW embedded processing. In ISCA, 2000.
14. R. E. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 20(2), 2000.
15. C. Hardnett, K. V. Palem, and Y. Chobe. Compiler optimization of embedded applications for an adaptive soc architecture. In CASES, 2006.
16. G. Karypis and V. Kumar. A fast and high quality multilevel scheme for partitioning irregular graphs. SIAM Journal on Scientific Computing, 20(1):359-392, 1998.
17. G. Karypis and V. Kumar. Multilevel k-way partitioning scheme for irregular graphs. Journal of Parallel and Distributed Computing, 48(1):96-129, 1998.
18. R. Kastner et al. Instruction generation for hybrid reconfigurable systems. ACM TODAES, 7(4), 2002.
19. M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss. An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications. In DAC, 1999.
20. B. W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. In The Bell System Technical Journal, volume 49(2), pages 291-307, 1970.
21. D. L. Kreher and D. R. Stinson. Combinatorial Algorithms Generation, Enumeration and Search. CRC Press Inc, 1998.
22. J. Lee, K. Choi, and N. Dutt. Efficient instruction encoding for automatic instruction set design of configurable asips. In ICCAD, 2002.
23. Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurkure, and J. Stockwood. Hardware-software co-design of embedded reconfigurable architectures. In DAC, 2000.
24. Z. Li and S. Hauck. Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. In FPGA, 2002.
25. C. G. Nevill-Manning and I. H. Witten. Identifying hierarchical structure in sequences: A linear-time algorithm. Journal Of Artificial Intelligence Research, 7:67-82, 1997.
26. K. M. G. Puma and D. Bhatia. Temporal partitioning and scheduling data flow graphs for reconfigurable computers. IEEE Transactions on Computers, 48(6):579-590, 1999.
27. Stretch Inc. Stretch S5530 software configurable processor.
28. N. Topham. Challenges to automatic customization. In P. Ienne and R. Leupers, editors, Customizable Embedded Processors. Morgan Kauffman, 2006.