-
1
-
-
0032656346
-
Dynamically reconfigurable architecture for image processing applications
-
A.M.S. Adario, E.L. Roehe, and S. Bampi, "Dynamically Reconfigurable Architecture for Image Processing Applications," Design Automation Conf., pp. 623-628, 1999.
-
(1999)
Design Automation Conf.
, pp. 623-628
-
-
Adario, A.M.S.1
Roehe, E.L.2
Bampi, S.3
-
2
-
-
0032660346
-
Nostradamus: A floorplanner of uncertain designs
-
K. Bazargan, S. Kim, and M. Sarrafzadeh, "Nostradamus: A Floorplanner of Uncertain Designs," IEEE Trans. Computer Aided Design, pp. 389-397, 1999.
-
(1999)
IEEE Trans. Computer Aided Design
, pp. 389-397
-
-
Bazargan, K.1
Kim, S.2
Sarrafzadeh, M.3
-
5
-
-
0031645164
-
Fast module mapping and placement for datapaths in FPGAs
-
Feb
-
T.J. Callahan, P. Chong, A. DeHon, and J. Wawrzynek, "Fast Module Mapping and Placement for Datapaths in FPGAs," Int'l ACM/SIGDA Symp. Field Programmable Gate Arrays, Feb. 1998.
-
(1998)
Int'l ACM/SIGDA Symp. Field Programmable Gate Arrays
-
-
Callahan, T.J.1
Chong, P.2
DeHon, A.3
Wawrzynek, J.4
-
6
-
-
0020797485
-
The bottom-left bin-packing heuristic: An efficient implementation
-
Aug
-
B. Chazelle, "The Bottom-Left Bin-Packing Heuristic: An Efficient Implementation," IEEE Trans. Computers, vol. 32, no. 8, pp. 697-707, Aug. 1983.
-
(1983)
IEEE Trans. Computers
, vol.32
, Issue.8
, pp. 697-707
-
-
Chazelle, B.1
-
7
-
-
0027316515
-
A buffer distribution algorithm for high-speed clock routing
-
J.D. Cho and M. Sarrafzadeh, "A Buffer Distribution Algorithm for High-Speed Clock Routing," Design Automation Conf., pp. 537-543, 1993.
-
(1993)
Design Automation Conf.
, pp. 537-543
-
-
Cho, J.D.1
Sarrafzadeh, M.2
-
8
-
-
0032668914
-
Embedded tutorial: Reconfigurable computing: What, why, and implications for design automation
-
A. DeHon and J. Wawrzynek, "Embedded Tutorial: Reconfigurable Computing: What, Why, and Implications for Design Automation," Design Automation Conf., pp. 610-615, 1999.
-
(1999)
Design Automation Conf.
, pp. 610-615
-
-
DeHon, A.1
Wawrzynek, J.2
-
9
-
-
0343513607
-
Splash: A reconfigurable linear logic array
-
M. Gokhale, B. Holmes, A. Kopser, D. Kunze, D. Lopresti, S. Lucas, R. Minnich, and P. Olsen, "Splash: A Reconfigurable Linear Logic Array," Int'l Conf. Parallel Processing, pp. 526-532, 1990.
-
(1990)
Int'l Conf. Parallel Processing
, pp. 526-532
-
-
Gokhale, M.1
Holmes, B.2
Kopser, A.3
Kunze, D.4
Lopresti, D.5
Lucas, S.6
Minnich, R.7
Olsen, P.8
-
10
-
-
0031643963
-
Configuration prefetch for single context reconfigurable coprocessors
-
Feb
-
S. Hauck, "Configuration Prefetch for Single Context Reconfigurable Coprocessors," Int'l ACM/SIGDA Symp. Field Programmable Gate Arrays, pp. 65-74, Feb. 1998.
-
(1998)
Int'l ACM/SIGDA Symp. Field Programmable Gate Arrays
, pp. 65-74
-
-
Hauck, S.1
-
11
-
-
0000950606
-
The roles of FPGAs in reprogrammable systems
-
Apr
-
S. Hauck, "The Roles of FPGAs in Reprogrammable Systems," Proc. IEEE, vol. 86, no. 4, pp. 615-638, Apr. 1998.
-
(1998)
Proc. IEEE
, vol.86
, Issue.4
, pp. 615-638
-
-
Hauck, S.1
-
12
-
-
0031376640
-
The chimaera reconfigurable functional unit
-
S. Hauck, T.W. Fry, M.M. Hosler, and J.P. Kao, "The Chimaera Reconfigurable Functional Unit," Proc. IEEE Symp. FPGAs for Custom Computing Machines, pp. 87-96, 1997.
-
(1997)
Proc. IEEE Symp. FPGAs for Custom Computing Machines
, pp. 87-96
-
-
Hauck, S.1
Fry, T.W.2
Hosler, M.M.3
Kao, J.P.4
-
13
-
-
84949274902
-
Configuration compression for the Xilinx XC6200 FPGA
-
S. Hauck, Z. Li, and E.J. Schwabe, "Configuration Compression for the Xilinx XC6200 FPGA," Proc. IEEE Symp. FPGAs for Custom Computing Machines, pp. 138-146, 1998.
-
(1998)
Proc. IEEE Symp. FPGAs for Custom Computing Machines
, pp. 138-146
-
-
Hauck, S.1
Li, Z.2
Schwabe, E.J.3
-
14
-
-
0012167822
-
-
Technical Report ULCSIS-97-1, Dept. of Computer Science and Information Systems, Univ. of Limerick, Limerick, Ireland
-
P. Healy and M. Creavin, "An Optimal Algorithm for Rectangle Placement," Technical Report ULCSIS-97-1, Dept. of Computer Science and Information Systems, Univ. of Limerick, Limerick, Ireland, 1997.
-
(1997)
An Optimal Algorithm for Rectangle Placement
-
-
Healy, P.1
Creavin, M.2
-
16
-
-
0002026363
-
Approximation algorithms for bin packing: A survey
-
D.S. Hochbaum, ed., Boston: PWS Publishing Company
-
E.G. Coffman, Jr., M.R. Garey, and D.S. Johnson, "Approximation Algorithms for Bin Packing: A Survey," D.S. Hochbaum, ed., Approximation Algorithms for NP-Hard Problems. Boston: PWS Publishing Company, 1997, pp. 46-93.
-
(1997)
Approximation Algorithms for NP-hard Problems
, pp. 46-93
-
-
Coffman E.G., Jr.1
Garey, M.R.2
Johnson, D.S.3
-
17
-
-
0027558279
-
Packings in two dimensions: Asymptotic average-case analysis of algorithms
-
Mar
-
E.G. Coffman, Jr., and P.W. Shor, "Packings in Two Dimensions: Asymptotic Average-Case Analysis of Algorithms," Algorithmica, vol. 9, no. 3, pp. 253-277, Mar. 1993.
-
(1993)
Algorithmica
, vol.9
, Issue.3
, pp. 253-277
-
-
Coffman E.G., Jr.1
Shor, P.W.2
-
20
-
-
0024611253
-
A doughnut layout style for improved switching speed with CMOS VLSI gates
-
C. Longway and R. Siferd, "A Doughnut Layout Style for Improved Switching Speed with CMOS VLSI Gates," IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 194-198, 1989.
-
(1989)
IEEE J. Solid-state Circuits
, vol.24
, Issue.1
, pp. 194-198
-
-
Longway, C.1
Siferd, R.2
-
23
-
-
51249179448
-
The average-case analysis of some on-line algorithms for bin packing
-
P.W. Shor, "The Average-Case Analysis of Some On-Line Algorithms for Bin Packing," Combinatorica, vol. 6, no. 2, pp. 179-200, 1986.
-
(1986)
Combinatorica
, vol.6
, Issue.2
, pp. 179-200
-
-
Shor, P.W.1
-
24
-
-
0029264395
-
Efficient and effective placement for very large circuits
-
Mar
-
W.J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits," IEEE Trans. Computer Aided Design, vol. 14, no. 3, pp. 349-359, Mar. 1995.
-
(1995)
IEEE Trans. Computer Aided Design
, vol.14
, Issue.3
, pp. 349-359
-
-
Sun, W.J.1
Sechen, C.2
-
26
-
-
0032593115
-
3-D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems
-
K. Bazargan, R. Kastner, and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems," 10th IEEE Int'l Workshop on Rapid System Prototyping, pp. 38-43, 1999.
-
(1999)
10th IEEE Int'l Workshop on Rapid System Prototyping
, pp. 38-43
-
-
Bazargan, K.1
Kastner, R.2
Sarrafzadeh, M.3
|