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Volumn , Issue , 2009, Pages 59-64

FSM-controlled architectures for linear invasion

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; MULTIPROCESSING SYSTEMS; SYSTEM-ON-CHIP;

EID: 80555145039     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2009.6041331     Document Type: Conference Paper
Times cited : (4)

References (16)
  • 3
    • 38549135754 scopus 로고    scopus 로고
    • Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: Architectural parameters and methodology
    • F. Hannig, H. Dutta, and J. Teich, "Mapping a Class of Dependence Algorithms to Coarse-Grained Reconfigurable Arrays: Architectural Parameters and Methodology," International Journal of Embedded Systems, vol. 2, no. 1, pp. 114-127, 2006.
    • (2006) International Journal of Embedded Systems , vol.2 , Issue.1 , pp. 114-127
    • Hannig, F.1    Dutta, H.2    Teich, J.3
  • 5
    • 77949370311 scopus 로고    scopus 로고
    • Invasive algorithms and architectures
    • J. Teich, "Invasive Algorithms and Architectures," it - Information Technology, vol. 50, no. 5, pp. 300-310, 2008.
    • (2008) It - Information Technology , vol.50 , Issue.5 , pp. 300-310
    • Teich, J.1
  • 10
    • 58849136300 scopus 로고    scopus 로고
    • Exploiting application data-parallelism on dynamically reconfigurable architectures: Placement and architectural considerations
    • S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 2, pp. 234-247, 2009.
    • (2009) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.17 , Issue.2 , pp. 234-247
    • Banerjee, S.1    Bozorgzadeh, E.2    Dutt, N.3
  • 11
    • 33646940730 scopus 로고    scopus 로고
    • A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware [Multimedia applications]
    • Proceedings
    • J. Resano, D. Mozos, and F. Catthoor, "A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [Multimedia Applications]," in Design, Automation and Test in Europe, 2005. Proceedings, 2005, pp. 106-111.
    • (2005) Design, Automation and Test in Europe, 2005 , pp. 106-111
    • Resano, J.1    Mozos, D.2    Catthoor, F.3
  • 13
    • 33644643030 scopus 로고    scopus 로고
    • Marching-pixels: A new organic computing paradigm for smart sensor processor arrays
    • ACM New York, NY, USA
    • D. Fey and D. Schmidt, "Marching-Pixels: A new Organic Computing Paradigm for Smart Sensor Processor Arrays," in Proceedings of the 2nd Conference on Computing Frontiers. ACM New York, NY, USA, 2005, pp. 1-9.
    • (2005) Proceedings of the 2nd Conference on Computing Frontiers , pp. 1-9
    • Fey, D.1    Schmidt, D.2
  • 16
    • 40349113716 scopus 로고    scopus 로고
    • CAPSULE: Hardware-assisted parallel execution of component-based programs
    • DC, USA
    • P. Palatin and O. Temam, "CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs," IEEE Computer Society Washington, DC, USA, pp. 247-258, 2006.
    • (2006) IEEE Computer Society Washington , pp. 247-258
    • Palatin, P.1    Temam, O.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.