A highly parameterizable parallel processor array architecture

Proceedings - 2006 IEEE International Conference on Field Programmable Technology, FPT 2006

Volumn , Issue , 2006, Pages 105-112

  Kissler, Dmitrij ^a   Hannig, Frank ^a   Kupriyanov, Alexey ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CLASSIFICATION (OF INFORMATION); COMPUTER HARDWARE; COST EFFECTIVENESS; PARAMETER ESTIMATION; PARAMETERIZATION; TOPOLOGY;

ARCHITECTURE TEMPLATE; FLEXIBILITY GAINS; INTERCONNECT TOPOLOGIES; SYSTEMATICAL CLASSIFICATION;

PARALLEL PROCESSING SYSTEMS;

EID: 38049182336     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2006.270293     Document Type: Conference Paper

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