Exploiting application data-parallelism on dynamically reconfigurable architectures: Placement and architectural considerations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 2, 2009, Pages 234-247

  Banerjee, Sudarshan ^a   Bozorgzadeh, Elaheh ^b   Dutt, Nikil ^b  

^a Liga Systems   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Dynamic reconfiguration; Program parallelization

Indexed keywords

APPLICATIONS; DYNAMIC MODELS; EMBEDDED SYSTEMS; INTEGER PROGRAMMING; LINEARIZATION; SCHEDULING;

APPLICATION DATUM; APPLICATION MAPPINGS; APPLICATION TASKS; DATA PARALLELISMS; DATA PARALLELS; DYNAMIC RECONFIGURATION; DYNAMICALLY RECONFIGURABLE ARCHITECTURES; EMBEDDED PROCESSORS; EXECUTION TIME; HIGH QUALITIES; INTEGER LINEAR PROGRAMMING FORMULATIONS; JOINT SCHEDULING; KEY FEATURES; ON-DEMAND COMPUTING; PARTIAL DYNAMIC RECONFIGURATIONS; PROGRAM PARALLELIZATION; RECONFIGURABLE PLAT-FORMS; RECONFIGURATION OVERHEADS; RESOURCE AVAILABILITIES; RUN-TIME; RUN-TIME RECONFIGURATIONS; SYNTHETIC EXPERIMENTS; TASK EXECUTIONS; TEST CASE;

DYNAMICAL SYSTEMS;

EID: 58849136300     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2003490     Document Type: Article

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