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Volumn I, Issue , 2005, Pages 106-111

A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of dynamically reconfigurable hardware

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RECONFIGURABLE HARDWARE (DRHW); MULTIMEDIA APPLICATIONS; RUN-TIME FLEXIBILITY;

EID: 33646940730     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.18     Document Type: Conference Paper
Times cited : (51)

References (12)
  • 1
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    • www.ipflex.com
  • 2
    • 84858936348 scopus 로고    scopus 로고
    • www.elixent.com
  • 3
    • 2642571809 scopus 로고    scopus 로고
    • Configuration management in multi-context reconfigurable systems
    • Maestre, R. et al, "Configuration Management in Multi-Context Reconfigurable Systems", ISSS'00, pp, 107-113, 2000.
    • (2000) ISSS'00 , pp. 107-113
    • Maestre, R.1
  • 4
    • 79955158088 scopus 로고    scopus 로고
    • Interconnection network enable fine-grain dynamic multi-tasking on FPGAs
    • Marescaux, T. et al., "Interconnection Network enable Fine-Grain Dynamic Multi-Tasking on FPGAs", FPL'02, pp. 795-805, 2002.
    • (2002) FPL'02 , pp. 795-805
    • Marescaux, T.1
  • 5
    • 84893813102 scopus 로고    scopus 로고
    • Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip
    • Mignolet, J-Y. et al. "Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip" DATE'03, pp. 986-991, 2003.
    • (2003) DATE'03 , pp. 986-991
    • Mignolet, J.-Y.1
  • 6
    • 4444369634 scopus 로고    scopus 로고
    • Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware
    • Resano, J. et al. "Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware". DAC'04, pp. 119-124, 2004.
    • (2004) DAC'04 , pp. 119-124
    • Resano, J.1
  • 7
    • 2642576803 scopus 로고    scopus 로고
    • A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs
    • Elsevier publishers
    • Resano, J. et al. "A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs". Journal on Microprocessors and Microarchitectures. Elsevier publishers. Volume 28, Issues 5-6, pp. 291-301, 2004.
    • (2004) Journal on Microprocessors and Microarchitectures , vol.28 , Issue.5-6 , pp. 291-301
    • Resano, J.1
  • 8
    • 84962312624 scopus 로고    scopus 로고
    • Hw/Sw Co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs
    • Shang, Li et al., "Hw/Sw Co-synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs", ASP-DAC02, pp. 345-360, 2002.
    • (2002) ASP-DAC02 , pp. 345-360
    • Shang, L.1
  • 9
    • 0035444245 scopus 로고    scopus 로고
    • Energy-aware runtime scheduling for embedded-multiprocessors SOCs
    • Yang, P. et al., "Energy-Aware Runtime Scheduling for Embedded-Multiprocessors SOCs", IEEE Design&Test of Computers, pp. 46-58, 2001.
    • (2001) IEEE Design&Test of Computers , pp. 46-58
    • Yang, P.1
  • 10
    • 1142275611 scopus 로고    scopus 로고
    • Pareto-optimization-based run-time task scheduling for embedded systems
    • Yang, P. et al "Pareto-Optimization-Based Run-Time Task Scheduling for Embedded Systems". ISSS'03, pp 120-125. 2003.
    • (2003) ISSS'03 , pp. 120-125
    • Yang, P.1
  • 11
    • 84858939370 scopus 로고    scopus 로고
    • www.xilinx.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.