MVP: Minimum-violations partitioning for reducing capture power in at-speed delay-fault testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 11, 2011, Pages 1762-1767

  Chen, Zhen ^a   Chakrabarty, Krishnendu ^b   Xiang, Dong ^a  

^a TSINGHUA UNIVERSITY   (China)

^b Duke University   (United States)

Author keywords

Capture power; delay testing; low power testing; minimum violations partitioning

Indexed keywords

AT-SPEED; BENCHMARK CIRCUIT; CAPTURE POWER; CLUSTERING METHODS; DELAY TESTING; DELAY-FAULT TESTING; FAULT COVERAGES; HIERARCHICAL PARTITIONING; INTEGER LINEAR PROGRAMMING MODELS; LOW POWER; MINIMUM-VIOLATIONS PARTITIONING; PARTITIONING METHODS; POWER REDUCTIONS; SCAN CELLS; SCAN FLIP-FLOPS; SHIFT CYCLES; TEST PATTERN; TEST-DATA VOLUME;

COMPUTER PROGRAMMING; FLIP FLOP CIRCUITS; INTEGER PROGRAMMING; SCANNING; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 80054797708     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2162237     Document Type: Article

References (19)

1. D. Berthelot, S. Chaudhuri, and H. Savoj, "An efficient linear time algorithm for scan chain optimization and repartitioning," in Proc. ITC, 2002, pp. 781-787.
2. D. Bertsimas and J. N. Tsitsiklis, Introduction to Linear Optimization. Belmont, MA: Athena Scientific, 1997.
3. Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, "Design of routing-constrained low power scan chains," in Proc. DATE, Feb. 2004, pp. 62-67.
4. K. M. Butler, "Minimizing power consumption in scan testing: Pattern generation and DFT techniques," in Proc. ITC, 2004, pp. 355-364.
5. M. Nourani, M. Tehranipoor, and N. Ahmed, "Low-transition test pattern generation for BIST-based applications," IEEE Trans. Comput., vol. 57, no. 3, pp. 303-315, Mar. 2008.
6. J. Chen, C. Yang, and K. J. Lee, "Test pattern generation and clock disabling for simultaneous test time and power reduction," IEEE Trans. Comput.-Aided Des., vol. 22, no. 3, pp. 363-370, Mar. 2003.
7. Z. Chen, K. Chakrabarty, and D. Xiang, "MVP: Capture-power reduction with minimum-violations partitioning for delay testing," in Proc. ICCAD, 2010, pp. 149-155.
8. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, "Low power BIST design by hypergraph partitioning: Methodology and architectures," in Proc. ITC, Oct. 2000, pp. 652-661.
9. H. F. Ko and N. Nicolici, "Automated scan chain division for reducing shift and capture power during broadside at-speed test," IEEE Trans. Comput.-Aided Des., vol. 27, no. 11, pp. 2092-2097, Nov. 2008.
10. K.-J. Lee, S.-J. Hsu, and C.-M. Ho, "Test power reduction with multiple capture orders," in Proc. Asian Test Symp., 2004, pp. 26-31.
11. J. Li, Q. Xu, Y. Hu, and X. Li, "iFill: An impact-oriented x-filling method for shift-and capture-power reduction in at-speed scan-based testing," in Proc. DATE, Mar. 2008, pp. 1184-1189.
12. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: Applications in VLSI domain," IEEE Trans. Very Large Scale Integr. Syst., vol. 7, no. 1, pp. 69-79, Mar. 1999.
13. P. Raghavan and C. D. Thompson, "Randomized rounding: A technique for provably good algorithms and algorithmic proofs," Combinatorica, vol. 7, no. 4, pp. 365-374, 1987.
14. S. Remersaro, X. Lin, Z. Zhang, S. M. Reddy, I. Pomeranz, and J. Rajski, "Preferred fill: A scalable method to reduce capture power for scan based designs," in Proc. ITC, no. 32.2. Oct. 2006, pp. 1-10.
15. P. Rosinger, B. M. Al-Hashimi, and N. Nicolici, "Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction," IEEE Trans. Comput.-Aided Des., vol. 23, no. 7, pp. 1142-1153, Jul. 2004.
16. J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, N. V. Arvind, P. Sreeprakash, and M. Hachinger, "A case study of IR-drop in structured at-speed testing," in Proc. ITC, 2003, pp. 1098-1104.
17. X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, W. Laung-Terng, K. K. Saluja, and K. Kinoshita, "Low-capture-power test generation for scan-based at-speed testing," in Proc. ITC, 2005, pp. 1019-1028.
18. Q. Xu, D. Hu, and D. Xiang, "Pattern-directed circuit virtual partitioning for test power reduction," in Proc. ITC, Oct. 2007, paper 25.2.
19. Z. Zhang, S. M. Reddy, I. Pomeranz, J. Rajski, and B. M. Al-Hashimi, "Enhancing delay fault coverage through low power segmented scan," in Proc. ETS, May 2006, pp. 21-28.