A leakage-aware L2 cache management technique for producerconsumer sharing in low-power chip multiprocessors

Journal of Parallel and Distributed Computing

Volumn 71, Issue 12, 2011, Pages 1545-1557

  Kim, Hyunhee ^a   Kim, Jihong ^a  

^a Seoul National University   (South Korea)

Author keywords

Chip multiprocessors; L2 cache; Leakage; Producerconsumer sharing

Indexed keywords

CACHE BLOCKS; CHIP MULTIPROCESSOR; L2 CACHE; LEAKAGE POWER MANAGEMENT; LOW POWER; MANAGEMENT TECHNIQUES; OFF-CHIP MEMORIES; ON-CHIP L2 CACHE; PERFORMANCE LOSS; PRODUCERCONSUMER SHARING; RUNTIMES; SHARED BUFFER; SHARED BUS; SPATIAL LOCALITY; TARGET APPLICATION;

CACHE MEMORY; EMBEDDED SYSTEMS; ENERGY UTILIZATION; INDUSTRIAL MANAGEMENT; LEAKAGE CURRENTS; MULTIPROCESSING SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 80054679382     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2011.08.006     Document Type: Article

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