Using coherence information and decay techniques to optimize L2 cache leakage in CMPs

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2009, Pages 1-8

  Monchiero, Matteo ^a   Canal, Ramon ^b   González, Antonio ^b  

^a Exascale Computing Lab   (United States)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Cache Decay; Chip multiprocessor; CMP; Coherence; Leakage; Multicore

Indexed keywords

CACHE DECAY; CACHE SIZE; CHIP MULTIPROCESSOR; COHERENCE INFORMATION; COHERENCE PROTOCOL; ENERGY REDUCTION; L2 CACHE; LEAKAGE OPTIMIZATION; MULTI CORE; PERFORMANCE LOSS; POWER SAVINGS;

CACHE MEMORY; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; OPTIMIZATION;

DECAY (ORGANIC);

EID: 77951496804     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2009.28     Document Type: Conference Paper

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