Adaptive Mode Control: A Static-Power-Efficient Cache Design

ACM Transactions on Embedded Computing Systems

Volumn 2, Issue 3, 2003, Pages 347-372

  Zhou, Huiyang ^a   Toburen, Mark C ^a   Rotenberg, Eric ^a   Conte, Thomas M ^a  

^a North Carolina State University   (United States)

Author keywords

adaptive mode control; Cache; Design; Experimentation; Performance; static power

Indexed keywords

EID: 0344841297     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/860176.860181     Document Type: Article

References (25)

1. Albonesi, D., 1999. Selective cache ways: On-demand cache resource allocation. In Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 32) (November), 248-259.
2. Bellas, N., Hajj, I., Polychropoulos, C., 1999. A detailed, transistor-level energy model for SRAM-based caches. In Proceedings of International Symposium on Circuits and Systems, vol. 6, 198-201.
3. Bellas, N., Hajj, I., Polychropoulos, C, Stamoulis, G., 2000. Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on VLSI Systems 8, 3, 317-326.
4. Borkar, S., 1999. Design challenges of technology scaling. IEEE Micro 19, 4 (July), 23-29.
5. Burger, D., Austin, T. M., 1997. The Simplescalar Tool Set Version 2.0. Tech. Rep., Computer Science Department, University of Wisconsin-Madison.
6. Butts, J. A., Sohi, G. S., 2000. A static power model for architects. In Proceedings of the 33rdAnnual IEEE/ACM International Symposium on Microarchitecture (MICRO 33) (December), 191-201.
7. Gonzalez, R., Horowitz, M., 1996. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits 31, 9, 1277-1284.
8. Gwennap, L., 1996. Digital 21264 sets new standard. Microprocessor Report 10, 14 (October).
9. Kamble, M. B., Ghose, K., 1997. Analytical energy dissipation models for low power caches. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED) (August), 143-148.
10. Kaxiras, S., Hu, Z., Martonosi, M., 2001. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of 28th International Symposium On Computer Architecture (ISCA) (June), 240-251.
11. Kaxiras, S., Hu, Z., Narlikar, G., Mclellan, R., 2000. Cache-line decay: A mechanism to reduce cache leakage power. IEEE Workshop on Power Aware Computer Systems (November).
12. Kin, J., Gupta, M., Mangione-Smith, W., 1997. The filter cache: An energy efficient memory structure. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 30) (November), 184-193.
13. Ko, U., Balsara, P. T., 1995. Characterization and design of A low-power, high-performance cache architecture. In Proceedings of International Symposium on VLSI Technology, Systems, and Applications, 235-238.
14. Kuroda, T., Fujita, T., Mita, S., Nagamatu, T., Yoshioka, S., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., Sakurai, T., 1996. A 0.9 V, 150 MHz 10 mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage scheme. IEEE Journal of Solid-State Circuits 31, 1770-1779.
15. Lee, H.-H.S., Tyson, G. S., Farrens, M. K., 2000. Eager writeback-A technique for improving bandwidth utilization. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 33) (December), 11-21.
16. Margala, M., 1999. Low power SRAM circuit design. In IEEE International Workshop on Memory Technology, Design, and Testing, 115-122.
17. Montanaro, J., Witek, R. T., Anne, K., Black, A. J., Cooper, E. M., Dobberpuhl, D. W., Donahue, P. M., Eno, J., Hoeppner, G. W., Kruckemyer, D., Lee, T. H., Lin, P. C. M., Madden, L., Murray, D., Pearce, M. H., Santhanam, S., Snyder, K. J., Stephany, R., Thierauf, S. C., 1997. A 160-MHZ, 32-B, 0.5-W CMOS RISC MICROPROCESSOR. Digital Technical Journal 9, 49-62.
18. Nii, K., Makino, H., Tujihashi, Y., Morishima, C., Hayakawa, Y., Nunogami, H., Arakawa, T., Hamano, H., 1998. A Low power SRAM using auto-backgate-bontrolled MT-CMOS. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 293-298.
19. Powell, M., Yang, S.-H., Falsafi, B., Roy, K., Vijaykumar, T., 2000. Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 90-95.
20. Reinman, G., Jouppi, N., 1999. An itegrated cache timing and power model. CACTI 2.0 Tech. Rep., COMPAQ Western Research Lab.
21. Shigematsu, S., Mutoh, S., Matsuya, Y., Tanabe, Y., Yamada, J., 1997. A 1-V high speed MTC-MOS circuit scheme for power-down application circuits. IEEE Journal of Solid-State Circuits 32, 861-869.
22. Vijaykrishnan, N., Kandemir, M., Irwin, M. J., Kim, H. S., Ye, W., 2000. Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower. In Proceedings of 27th International Symposium on Computer Architecture (ISCA) (June), 95-106.
23. Yang, S.-H., Powell, M., Falsafi, B., Roy, K., Vijaykumar, T., 2001. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA) (January), 147-157.
24. Ye, Y., Borkar, S., De, V., 1998. A new technique for standby leakage reduction in high performance circuits. In IEEE Symposium on VLSI Circuits, 40-41.
25. Zhou, H., Toburen, M., Rotenberg, E., Conte, T. M., 2000. AMC: ALow Leakage Power Efficient On-chip Cache System Design. Tech. Rep., Department of Electrical and Computer Engineering, North Carolina State University.