Replication-aware leakage management in chip multiprocessors with private L2 caches

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2010, Pages 135-140

  Kim, Hyunhee ^a   Ho Ahn, Jung ^a   Kim, Jihong ^a  

^a Seoul National University   (South Korea)

Author keywords

Chip multiprocessors; L2 caches; Leakage power manage ment

Indexed keywords

CACHE COHERENCE; CACHE MISS; CHIP MULTIPROCESSOR; COHERENCE STATE; CRITICAL ISSUES; ENERGY CONSUMPTION; IN-CHIP; L2 CACHE; LEAKAGE POWER; LEAKAGE POWER REDUCTION; LOW POWER; MAIN MEMORY; MANAGEMENT TECHNIQUES; OFF-CHIP MEMORIES; ON-CHIP CACHE; PERFORMANCE LOSS; POWER DISSIPATION; PROCESS TECHNOLOGIES; TOTAL POWER DISSIPATION;

ELECTRIC LOSSES; ENERGY UTILIZATION; IMAGE CODING; INDUSTRIAL MANAGEMENT; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; POWER ELECTRONICS;

CACHE MEMORY;

EID: 77957959177     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1840845.1840874     Document Type: Conference Paper

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