Improved device performance by post-oxide annealing in atomic-layer- deposited Al2O3/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor on Si

Applied Physics Express

Volumn 4, Issue 10, 2011, Pages

  Zhou, Hong ^a   Ng, Geok Ing ^a   Liu, Zhi Hong ^a   Arulkumaran, Subramaniam ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC LAYER DEPOSITED; DC PERFORMANCE; DEEP LEVEL TRAP; DEVICE PERFORMANCE; FORWARD CURRENTS; GATE DRAIN; HIGH-RESISTIVITY SILICON SUBSTRATE; INTERFACE STATE; MAXIMUM TRANSCONDUCTANCE; METAL INSULATORS; METAL-INSULATOR-SEMICONDUCTORS;

ALUMINUM; ANNEALING; ELECTRON MOBILITY; GALLIUM NITRIDE; HIGH ELECTRON MOBILITY TRANSISTORS; METAL INSULATOR BOUNDARIES; MIS DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR INSULATOR BOUNDARIES; TRANSISTORS;

METAL ANALYSIS;

EID: 80054065355     PISSN: 18820778     EISSN: 18820786     Source Type: Journal    
DOI: 10.1143/APEX.4.104102     Document Type: Article

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