On the skew-bounded minimum-buffer routing tree problem

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 7, 2003, Pages 937-945

  Albrecht, Christoph ^a   Kahng, Andrew B ^b,c   Liu, Bao ^c,d   Mǎndoiu, Ion I ^e   Zelikovsky, Alexander Z ^f  

^a UNIVERSITY OF BONN   (Germany)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e Georgia State University ^*  (United States)

^f GEORGIA STATE UNIVERSITY   (United States)

Author keywords

Algorithms; Buffer insertion; Buffer skew; Dynamic programming; Interconnect design

Indexed keywords

ALGORITHMS; CAPACITANCE; DIGITAL INTEGRATED CIRCUITS; DYNAMIC PROGRAMMING; LOGIC GATES; SPURIOUS SIGNAL NOISE; THEOREM PROVING; VLSI CIRCUITS;

BUFFER SKEW; LOAD CAPACITANCE; ROUTING TREE PROBLEM;

LOGIC DESIGN;

EID: 0038444625     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.814238     Document Type: Article

References (12)

1. C. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 588-593.
2. C. Alpert, A. B. Kahng, B. Liu, I. I. Mǎndoiu, and A. Z. Zelikovsky, "Minimum-buffered routing for slew and reliability control," in Proc. IEEE-ACM Int. Conf. Computer-Aided Design, 2001, pp. 408-415.
3. M. Edahiro, "Delay minimization for zero-skew routing," in Proc. IEEE-ACM Int. Conf. Computer-Aided Design, 1993, pp. 563-567.
4. P. Fang, J. Tao, J. F. Chen, and C. Hu, "Design in hot-carrier reliability for high performance logic applications," in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 525-532.
5. C. Hu, "Hot carrier effects," in Advanced MOS Device Physics, N. G. Einspruch, Ed. New York: Academic, 1989, pp. 119-160.
6. A. B. Kahng, S. Muddu, E. Sarto, and R. Sharma, "Interconnect tuning strategies for high-performance ICs," in Proc. Conf. Design Automation Test Eur., Feb. 1998, pp. 471-478.
7. J. Lillis, C.-K. Cheng, and T.-T. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE J. Solid-State Circuits, vol. 31, pp. 437-447, 1996.
8. S. Rzepka, K. Banerjee, and E. Meusel, "Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation," IEEE Trans. Comp., Packag., Manufact. Technol. A, 21, pp. 406-411, Sept. 1998.
9. L. Scheffer, private communication, Apr. 2000.
10. G. E. Tellez and M. Sarrafzadeh, "Minimal buffer insertion in clock trees with skew and slew rate constraints," IEEE Trans. Computer-Aided Design, vol. 16, pp. 333-342, Apr. 1997.
11. L. P.P.P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. IEEE Int. Symp. Circuits Syst., 1990, pp. 865-868
12. A. Z. Zelikovsky and I. I. Mǎndoiu, "Practical approximation algorithms for zero- and bounded-skew trees," SIAM J. Discrete Math., vol. 15, no. 1, pp. 97-111, 2002.