Pre-bond testable low-power clock tree design for 3D stacked ICs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 184-190

  Zhao, Xin ^a   Lewis, Dean L ^a   Lee, Hsien Hsin S ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK DISTRIBUTION NETWORKS; CLOCKS; COMPUTER AIDED DESIGN; DIES; ELECTRIC POWER UTILIZATION; ELECTRONICS PACKAGING; FORESTRY; INTEGRATED CIRCUIT DESIGN; SPICE; TIMING CIRCUITS;

CLOCK POWER CONSUMPTION; LOW POWER CLOCK; NORMAL OPERATIONS; POST-BOND TESTING; SPICE SIMULATIONS; TESTABILITY; THROUGH-SILICON-VIA (TSV); WIRE LENGTH;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 76349084267     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1687399.1687433     Document Type: Conference Paper

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