8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 169-174

  Chiu, Yi Wei ^a   Lin, Jihi Yu ^a   Tu, Ming Hsien ^a   Jou, Shyh Jye ^a   Chuang, Ching Te ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Data Aware Write Operation; SRAM; Static Random Access Memory

Indexed keywords

ACTIVE POWER; BIT-INTERLEAVING; CELL FEATURES; CMOS TECHNOLOGY; LOW POWER; LOW VOLTAGE OPERATION; LOW VOLTAGES; PULSE WIDTH; SINGLE-ENDED; SRAM CELL; STATIC RANDOM ACCESS MEMORY; SUB-THRESHOLD SRAM; TEST CHIPS; TIMING VARIATIONS; WRITE OPERATIONS; WRITE STRUCTURE;

CMOS INTEGRATED CIRCUITS; ELECTRONIC CIRCUIT TRACKING; LOW POWER ELECTRONICS; MEMORY ARCHITECTURE; POWER ELECTRONICS; THRESHOLD VOLTAGE; TIMING CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 80052710738     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993631     Document Type: Conference Paper

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