OUTRIDER: Efficient memory latency tolerance with decoupled strands

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 117-128

  Crago, Neal C ^a   Patel, Sanjay J ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Accelerator; Computer architecture; Memory latency

Indexed keywords

ACCELERATOR; DATA PARALLEL; HARDWARE THREADS; IMPROVED AREA; INSTRUCTION STREAMS; LOW-COMPLEXITY; MEMORY LATENCIES; MICRO ARCHITECTURES; MULTITHREADED; OUT OF ORDER; PERFORMANCE GAIN; PROCESSOR PIPELINES; SINGLE-THREADED;

PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS; COMPUTER ARCHITECTURE; PARTICLE ACCELERATORS;

MEMORY ARCHITECTURE;

EID: 80052534264     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000079     Document Type: Conference Paper

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