Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 1699-1702

  Magnone, Paolo ^a   Crupi, Felice ^a   Alioto, Massimo ^b,c   Kaczer, Ben ^d  

^a UNIVERSITY OF CALABRIA   (Italy)

^b UNIVERSITY OF SIENA   (Italy)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BODY BIASING; COMPATIBLE PROCESS; EXPERIMENTAL MEASUREMENTS; EXPERIMENTAL STUDIES; FIGURES OF MERITS; JUNCTION LEAKAGES; MAIN CIRCUIT PARAMETER; METAL GATE; MOSFETS; P-MOSFETS; SI DEVICES; STACK EFFECT; STACK FORCING; STANDBY-POWER DISSIPATION; SYSTEM LEVELS; VLSI DESIGN;

DELAY CIRCUITS; DRAIN CURRENT; ELECTRIC NETWORK ANALYSIS; FABRICS; GERMANIUM; HOLE MOBILITY; MOSFET DEVICES; SILICON; SWITCHING CIRCUITS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 77955990527     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537514     Document Type: Conference Paper

References (9)

1. International Technology Roadmap for Semiconductors. From 2003 to 2007 Edition. available at http://public.itrs.net.
2. G. Nicholas, B. D. Jaeger, D. P. Brunco, P. Zimmerman, G. Eneman, K. Martens, M. Meuris, M. Heyns, "High-performance deep submicron Ge pMOSFETs with halo implants", IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2503-2511, 2007.
3. G. Eneman, O. Sicart i Casain, E. Simoen, D. P. Brunco, B. De Jaeger, A. Satta, G. Nicholas, C. Claeys, M. Meuris, M. M. Heyns, "Analysis of junction leakage in advanced germanium p+/n junctions," in Proc. ESSDERC, Munich (Germany), D. Schmitt-Landsiedel and R. Thewes, Eds., Sep. 11 13, 2007, pp. 454 457.
4. J. Mitard, B. De Jaeger, F.E. Leys, G. Hellings, K. Martens, G. Eneman, D.P. Brunco, R. Loo, J.C. Lin, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, C.H. Yu, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, M. Heyns, "Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability", IEEE IEDM Tech. Dig., pp. 1-4, 2008.
5. K. Martens, J. Mitard, B. De Jaeger, M. Meuris, H. Maes, F. Minucci, F. Crupi, G. Groeseneken, "Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs", European Solid- State Device Research Conference, pp. 138-141, 2008.
6. P. Magnone, F. Crupi, G. Giusi, C.Pace, E. Simoen, C. Claeys, L. Pantisano, D. Maji, V. Ramgopal Rao, P. Srinivasan, "1/f noise in drain and gate current of MOSFETs with high-k gate stacks" IEEE Trans. Device Mater. Reliab., vol. 9, no. 2, pp. 180-189, 2009.
7. P. Magnone, F. Crupi, M. Alioto, B. Kaczer, "Understanding the potential and the limits of Germanium pMOSFETs for VLSI circuits from experimental measurements", submitted on IEEE Trans. on VLSI Systems.
8. S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0 18-μm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 501 510, Mar. 2004.
9. M. Agostinelli, M. Alioto, D. Esseni, L. Selmi, "Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk Technology," in print on IEEE Trans. on VLSI Systems (available at http //ieeexplore.ieee.org)