Critical new issues relating to interfacial reactions arising from low solder volume in 3D IC packaging

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1723-1728

  Chuang, H Y ^a   Chen, W M ^a   Shih, W L ^a   Lai, Y S ^b   Kao, C R ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AGING PROCESS; AGING TIME; ELECTROPLATING PROCESS; GROWTH CURVES; HIGH-TEMPERATURE STORAGE; IC PACKAGING; INTERFACIAL AREAS; ISOTHERMAL AGING; MICROSTRUCTURE CHARACTERIZATION; PARABOLIC KINETICS; POWER LAW EXPONENT; POWER-LAW RELATIONSHIP; SOLDER VOLUME; VOLUME DIFFUSION;

GRAIN GROWTH; GROWTH KINETICS; MICROSTRUCTURE; PHASE INTERFACES; PROCESS CONTROL; THREE DIMENSIONAL;

TIN;

EID: 79960427760     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898744     Document Type: Conference Paper

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