First integration of Cu TSV using die-to-wafer direct bonding and planarization

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Leduc, Patrick ^a   Assous, Myriam ^a   Di Cioccio, Léa ^a   Zussy, Marc ^a   Signamarcheix, Thomas ^a   Roman, Antonio ^a   Rousseau, Maxime ^b   Verrun, Sophie ^a   Bally, Laurent ^a   Bouchu, David ^a   Cadix, Lionel ^b   Farcy, Alexis ^b   Sillon, Nicolas ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

3D integration; Die to wafer stacking; TSV

Indexed keywords

3-D ICS; 3D INTEGRATION; DIRECT BONDING; ELECTRICAL PERFORMANCE; HIGH DENSITY; MORPHOLOGICAL PROPERTIES; ON CHIPS; PLANARIZATION; PLANARIZATION TECHNIQUE; SUBSTRATE THINNING; WAFER DIRECT BONDING; WAFER STACKING; WAFER TEST;

DIES; ELECTRIC PROPERTIES; INTEGRATION; SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 70549104802     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306602     Document Type: Conference Paper

References (5)

1. P. Gueguen et al., MRS fall meeting, Proc. Vol. 1112, Boston, USA, Dec 1-5, 2008
2. P. Leduc, L. Di cioccio et al, VLSI 2008, proc.p.76-78 (2008)
3. P. Leduc et al, MRS fall meeting, Proc. Vol. 1112, Boston, USA, Dec 1-5, 2008
4. L. Di Cioccio et al. IEEE 3D Conference, San Francisco, USA, Sept 28-30, 2009
5. L. Cadix et al., MAM conference, Grenoble, France, March 8-11, 2009