Experimental investigation of bare silicon wafer warp

IEEE Workshop on Microelectronics and Electron Devices, WMED: IEEE Electron Devices Northwest Regional Meeting

Volumn , Issue , 2004, Pages 120-123

  Draney, Nathan R ^a   Liu, Jun Jun ^b   Jiang, Tom ^a  

^a MICRON TECHNOLOGY INC   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIAMONDS; ELECTRONICS PACKAGING; GRINDING (COMMINUTION); IMAGE ANALYSIS; INTEGRATED CIRCUITS; POLYIMIDES; THERMAL STRESS; TRANSMISSION ELECTRON MICROSCOPY;

BACKSIDE TENSION; METAL DENSITY; METAL LAYERS; WAFER WARP;

SILICON WAFERS;

EID: 3042608715     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/wmed.2004.1297371     Document Type: Conference Paper

References (3)

1. J. J. Young, A. P. Malsllie, W.D. Brown, Timothy Lenihan, Douglas Albert, Volkan Ozguz, "Thermal Modeling and Mechanical Analysis of Very Thin Silicon Chips for Conformal Electronic System," HD International Conference and Exposition on High Density Interconnects and System Packaging. Santa Clara, CA, April 2001.
2. J. Chen and I. De Wolf, "Study of Damage and Stress Induced by Backgrinding in Si Wafers," Semiconductor Science and technology, Vol. 18, pp.267-268, Febuary 2003.
3. M. Reiche and G. Wagner, "Wafer Thinning: Techniques for Ultra-thin Wafers," Advanced Packaging, March 2003.