-
1
-
-
28044443142
-
Thermal stresses in 3D IC inter-wafer interconnects
-
Jing Zhang, et al., "Thermal stresses in 3D IC inter-wafer interconnects", Microelectronic Engineering, Vol. 82, pp. 534-547, 2005.
-
(2005)
Microelectronic Engineering
, vol.82
, pp. 534-547
-
-
Zhang, J.1
-
2
-
-
84932091860
-
Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric
-
Phoenix, Arizona, April 25-29, pp
-
R.G. Filippi, et al., "Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric", Proceedings of the 2004 IEEE International Reliability Physics Symposium, Phoenix, Arizona, April 25-29, pp. 61-67, 2004.
-
(2004)
Proceedings of the 2004 IEEE International Reliability Physics Symposium
, pp. 61-67
-
-
Filippi, R.G.1
-
3
-
-
3042557048
-
Packaging effect on reliability of Cu/low-k interconnects
-
Guotao Wang, et al., "Packaging effect on reliability of Cu/low-k interconnects", IEEE Transactions on Devices and Materials Reliability, Vol. 3, No. 4, pp. 119-128, 2003.
-
(2003)
IEEE Transactions on Devices and Materials Reliability
, vol.3
, Issue.4
, pp. 119-128
-
-
Wang, G.1
-
4
-
-
33244479400
-
Thermo-mechanical stresses in copper interconnects - A modeling analysis
-
Y.L. Shen, "Thermo-mechanical stresses in copper interconnects - A modeling analysis", Microelectronic Engineering, Vol. 83, pp. 446-459, 2006.
-
(2006)
Microelectronic Engineering
, vol.83
, pp. 446-459
-
-
Shen, Y.L.1
-
5
-
-
0012039548
-
-
San Jose, Aug.-Sep, pp
-
Y. Tsukada and Y. Mashimoto, Proc. Surface Mount Intl., San Jose, Aug.-Sep., pp.294-299, 1992.
-
(1992)
Proc. Surface Mount Intl
, pp. 294-299
-
-
Tsukada, Y.1
Mashimoto, Y.2
-
6
-
-
49249134568
-
Investigation of interfacial delamination for Cu/low-k structures during flip-chip package
-
Guotao Wang, et al., "Investigation of interfacial delamination for Cu/low-k structures during flip-chip package", IEEE Inter Society Conference on Thermal Phenomena, pp.221-218, 2004
-
(2004)
IEEE Inter Society Conference on Thermal Phenomena
, pp. 221-218
-
-
Wang, G.1
-
7
-
-
0000560384
-
Analytical Assessment on the Effectiveness of Thermal Vias in Cooling Multichip Modules
-
K. Hisano, et al," Analytical Assessment on the Effectiveness of Thermal Vias in Cooling Multichip Modules," Proc of ASME/JSME Thermal Engineering Conference, Vol. 4, pp.193-198, 1995.
-
(1995)
Proc of ASME/JSME Thermal Engineering Conference
, vol.4
, pp. 193-198
-
-
Hisano, K.1
-
8
-
-
0034835759
-
Thermal Characterization of Bare-die Stacked Modules with Cu through-vias
-
Yamaji. Yasuhiro, et al," Thermal Characterization of Bare-die Stacked Modules with Cu through-vias," Proc of IEEE Electronic Components and Technology Conference, 2001.
-
(2001)
Proc of IEEE Electronic Components and Technology Conference
-
-
-
9
-
-
28444437438
-
Design of double layer WLCSP using DOE with factorial analysis technology
-
Singapore, December 8-10, pp
-
Chang-Chun Lee, Shu-Ming Chang, Kuo-Ning Chiang, "Design of double layer WLCSP using DOE with factorial analysis technology" Proceedings of 6th Electronics Packaging Technology Conference (EPTC), Singapore, December 8-10, pp. 776-781, 2004.
-
(2004)
Proceedings of 6th Electronics Packaging Technology Conference (EPTC)
, pp. 776-781
-
-
Lee, C.-C.1
Chang, S.-M.2
Chiang, K.-N.3
-
10
-
-
33846326485
-
Thermo-mechanical reliability study of high I/O flip chip on laminated substrate based on FEA, RSM and interfacial fracture mechanics
-
China, August 30-September 2, pp
-
Yingjun Cheng, et al., "Thermo-mechanical reliability study of high I/O flip chip on laminated substrate based on FEA, RSM and interfacial fracture mechanics", Proceedings of the 2005 IEEE International Conference on Electronic Packaging Technology, China, August 30-September 2, pp. 1-7, 2005.
-
(2005)
Proceedings of the 2005 IEEE International Conference on Electronic Packaging Technology
, pp. 1-7
-
-
Cheng, Y.1
-
11
-
-
40449086931
-
DOE analysis of effects of geometry and materials on Cu/low-k interconnect stresses
-
Vancouver, British Columbia, Canada, July 8-12
-
Ming-Che Hsieh and Wei Lee, "DOE analysis of effects of geometry and materials on Cu/low-k interconnect stresses", Proceeding of InterPACK 2007, Vancouver, British Columbia, Canada, July 8-12, 2007.
-
(2007)
Proceeding of InterPACK
-
-
Hsieh, M.-C.1
Lee, W.2
-
13
-
-
0031076104
-
Thermal Limits of Flip Chip Package-Experimentally Validated, CFD Supported Case Studies
-
Tien-Yu Lee, "Thermal Limits of Flip Chip Package-Experimentally Validated, CFD Supported Case Studies", IEEE Transaction on components and Packaging Technologies, Vol. 20, No. 1, pp.94-103, 1997.
-
(1997)
IEEE Transaction on components and Packaging Technologies
, vol.20
, Issue.1
, pp. 94-103
-
-
Lee, T.-Y.1
-
14
-
-
49249093515
-
-
All published JEDEC thermal standards are available for download at no charge on organization's web site (www.jedec.org)
-
All published JEDEC thermal standards are available for download at no charge on organization's web site (www.jedec.org)
-
-
-
-
15
-
-
0029705925
-
-
D. Edwards, Development of JEDEC standard thermal measurement test proceedings, SEMI-THERM XII conference, pp. 183-190, 1996.
-
D. Edwards, "Development of JEDEC standard thermal measurement test proceedings, SEMI-THERM XII conference, pp. 183-190, 1996.
-
-
-
-
16
-
-
0003486756
-
-
John Wiley & Sons, Inc, fifth edition, New York
-
D. C. Montgomery, "Design and Analysis of Experiments", John Wiley & Sons, Inc., fifth edition, New York, 2003.
-
(2003)
Design and Analysis of Experiments
-
-
Montgomery, D.C.1
-
17
-
-
0004236701
-
-
second edition, New York, Wiley, pp
-
W. G. Cochran and G. M. Cox, Experimental Designs, second edition, New York, Wiley, pp. 346-354, 1957.
-
(1957)
Experimental Designs
, pp. 346-354
-
-
Cochran, W.G.1
Cox, G.M.2
|