Reducing network-on-chip energy consumption through spatial locality speculation

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 233-240

  Kim, Hyungjun ^a   Ghoshal, Pritha ^a   Grot, Boris ^b   Gratz, Paul V ^a   Jiménez, Daniel A ^c  

^a Texas A and M University   (United States)

^b University of Texas at Austin   (United States)

^c Science Building   (United States)

Author keywords

cache design; Flit encoding

Indexed keywords

CACHE DESIGN; DATA PATHS; ENERGY MODEL; ENERGY OPTIMIZATION; ENERGY TARGETS; FLIT ENCODING; MEMORY SUBSYSTEMS; MICROARCHITECTURAL MECHANISM; MICROARCHITECTURAL SUPPORT; NETWORK ACTIVITIES; NETWORK ON CHIP; PERFORMANCE IMPACT; PERFORMANCE STUDY; PROCESSOR CHIPS; ROOT CAUSE; ROUTER DESIGN; SIMULATION-BASED; SPATIAL LOCALITY; SWITCHING ACTIVITIES;

COMPUTER SIMULATION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

ROUTERS;

EID: 79960296144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999983     Document Type: Conference Paper

References (32)

1. International Technology Roadmap for Semiconductors (ITRS) Working Group, "International Technology Roadmap for Semiconductors (ITRS), 2009 Edition." http://www.itrs.net/Links/2009ITRS/Home2009.htm.
2. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," in The 38th International Design Automation Conference (DAC), 2001.
3. Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, "A 5-GHz Mesh Interconnect for a Teraflops Processor," IEEE Micro, vol. 27, 2007.
4. M. Taylor, M. B. Taylor, W. Lee, S. Amarasinghe, and A. Agarwal, "Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures," in The IEEE International Symposium on High Performance Computer Architecture (HPCA), 2002.
5. D. Molka, D. Hackenberg, R. Schone, and M. S. Muller, "Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System," in The 18th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2009.
6. Advanced Micro Devices (AMD) Inc., "AMD Opteron Processors for Servers: AMD64-Based Server Solutions for x86 Computing." http://www.amd.com/us-en/Processors/ProductInformation/0,,30-118-8796,00.html.
7. P. Pujara and A. Aggarwal, "Cache Noise Prediction," IEEE Transactions on Computers, vol. 57, 2008.
8. C. Bienia, S. Kumar, J. P. Singh, and K. Li, "The PARSEC Benchmark Suite: Characterization and Architectural Implications," in The 17th International Conference on Parallel Architectures and Compilation Techniques, 2008.
9. L. Shang, L.-S. Peh, and N. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in High-Performance Computer Architecture, 2003.
10. A. B. Kahng, B. Li, L.-S. Peh, and K. Samadi, "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," in In The Design, Automation & Test in Europe Conference & Exhibition (DATE), 2009.
11. A. Banerjee, R. Mullins, and S. Moore, "A Power and Energy Exploration of Network-on-Chip Architectures," in The First International Symposium on Networks-on-Chip, 2007.
12. R. Das, A. Mishra, C. Nicopoulos, D. Park, V. Narayanan, R. Iyer, M. Yousif, and C. Das, "Performance and power optimization through data compression in network-on-chip architectures," in High Performance Computer Architecture, 2008. IEEE 14th International Symposium on.
13. Y. Jin, K. H. Yum, and E. J. Kim, "Adaptive data compression for high-performance low-power on-chip networks," in The 41st annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2008.
14. H. Zhang, V. George, and J. Rabaey, "Low-swing on-chip signaling techniques: effectiveness and robustness," IEEE Transactions on VLSI Systems, vol. 8, no. 3, 2000.
15. D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, "Low-power, high-speed transceivers for network-on-chip communication," IEEE Transactions on VLSI Systems, vol. 17, no. 1, 2009.
16. K. Hale, B. Grot, and S. Keckler, "Segment gating for static energy reduction in networks-on-chip," in Network on Chip Architectures, 2009. 2nd International Workshop on.
17. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2003.
18. S. Carr, K. S. McKinley, and C.-W. Tseng, "Compiler Optimizations for Improving Data Locality," SIGPLAN Notices, vol. 29, no. 11, 1994.
19. B. Calder, C. Krintz, S. John, and T. Austin, "Cache-Conscious Data Placement," in The 8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1998.
20. T. M. Chilimbi, B. Davidson, and J. R. Larus, "Cache-Conscious Structure Definition," SIGPLAN Notices, vol. 34, no. 5, 1999.
21. T. Chilimbi, M. Hill, and J. Larus, "Making Pointer-Based Data Structures Cache Conscious," IEEE Computer, vol. 33, no. 12, 2000.
22. J. S. Liptay, "Structural aspects of the System/360 Model 85, II: The cache," IBM Systems Journal, vol. 7, no. 1, 1968.
23. M. K. Qureshi, M. A. Suleman, and Y. N. Patt, "Line distillation: Increasing cache capacity by filtering unused words in cache lines," High-Performance Computer Architecture, International Symposium on, vol. 0, 2007.
24. A.-C. Lai, C. Fide, and B. Falsafi, "Dead-block prediction & dead-block correlating prefetchers," SIGARCH Comput. Archit. News, vol. 29, no. 2, 2001.
25. C. F. Chen, S. hyun Yang, and B. Falsafi, "Accurate and complexity-effective spatial pattern prediction," in In HPCA-10, IEEE Computer Society, 2004.
26. C. Kim, D. Burger, and S. W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," in ACM SIGPLAN NOTICES, 2002.
27. E. Jacobsen, E. Rotenberg, and J. E. Smith, "Assigning confidence to conditional branch predictions," in Proceedings of the 29th Annual International Symposium on Microarchitecture, 1996.
28. Intel, "Intel Atom Processor Z510." http://ark.intel.com/ Product.aspx?id=35469&processor=Z510&spec-codes=SLB2C.
29. Jon Stokes, "IBM's 8-core POWER7: twice the muscle, half the transistors." http://arstechnica.com/hardware/news/2009/09/ibms-8-core- power7-twice-the-muscle-half-the-transistors.ars.
30. N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "Optimizing nuca organizations and wiring alternatives for large caches with cacti 6.0," in Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, (Washington, DC, USA), IEEE Computer Society, 2007.
31. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, "The M5 Simulator: Modeling Networked Systems," IEEE Micro, vol. 26, 2006.
32. M. Gebhart, J. Hestness, E. Fatehi, P. Gratz, and S. W. Keckler, "Running PARSEC 2.1 on M5," tech. rep., The Univ. of Texas at Austin, Dept. of Comp. Sci., 2009.