Towards manufacturing of advanced logic devices by double-patterning

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7973, Issue , 2011, Pages

  Koay, Chiew Seng ^a   Halle, Scott ^a   Holmes, Steven ^a   Petrillo, Karen ^a   Colburn, Matthew ^a   Van Dommelen, Youri ^b   Jiang, Aiqin ^b   Crouse, Michael ^b   Dunn, Shannon ^c   Hetzer, David ^d   Kawakami, Shinichiro ^d   Cantone, Jason ^c   Huli, Lior ^e   Rodgers, Martin ^e   Martinick, Brian ^e  

^a IBM   (United States)

^b ASML US Inc   (United States)

^c TOKYO ELECTRON AMERICA INC   (United States)

^d TEL TECHNOLOGY CENTER   (United States)

^e STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

22nm node; 32 nm half pitch; CD optimizer; CDU; DoseMapper; Double patterning; Manufacturability; Overlay

Indexed keywords

22NM NODE; 32 NM HALF PITCH; CD-OPTIMIZER; CDU; DOSEMAPPER; DOUBLE PATTERNING; MANUFACTURABILITY; OVERLAY;

EXTREME ULTRAVIOLET LITHOGRAPHY; LITHOGRAPHY; LOGIC DEVICES; MANUFACTURE; NANOTECHNOLOGY; PHOTORESISTS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS;

SEMICONDUCTOR DEVICES;

EID: 79959241251     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.879618     Document Type: Conference Paper

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