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Volumn 6924, Issue , 2008, Pages

Alternative process schemes for double patterning that eliminate the intermediate etch step

Author keywords

32nm node; Alternative process flows; Double exposure; Double patterning; Dual development; Freezing; Novel materials

Indexed keywords

CLADDING (COATING); FREEZING; PIGMENTS;

EID: 45449094183     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.771884     Document Type: Conference Paper
Times cited : (47)

References (12)
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    • M. Maenhoudt, J. Versluijs, H. Struyf, J. Van Olmen, M. Van Hove, "Double patterning scheme for sub-0.25 k1single damascene structures at NA=0.75, λ=193nm", Proc. SPIE, 5754, p. 1508-1518, 2005.
    • (2005) Proc. SPIE , vol.5754 , pp. 1508-1518
    • Maenhoudt, M.1    Versluijs, J.2    Struyf, H.3    Van Olmen, J.4    Van Hove, M.5
  • 5
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  • 6
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    • Sub-100nm Lithography with KrF exposure using multiple development method
    • M. Asano, "Sub-100nm Lithography with KrF exposure using multiple development method", Jpn. J. Appl. Phys. Vol. 38, (1999), 6999-7003.
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    • Asano, M.1
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    • S. Tarutani et al., Proc SPIE, 6923, 6923-14, 2008.
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    • Tarutani, S.1
  • 9
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    • Hori, M.1
  • 10
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    • Martin Drapeau, et al., Double patterning design split implementation and validation fro the 32-nm node, SPIE 6521-07, 2007.
    • Martin Drapeau, et al., "Double patterning design split implementation and validation fro the 32-nm node", SPIE 6521-07, 2007.
  • 11
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    • Double patterning EDA solutions for the 32-nm HP and beyond
    • George Bailey, et al., "Double patterning EDA solutions for the 32-nm HP and beyond", SPIE 6521-57, 2007.
    • (2007) SPIE , vol.6521 -57
    • Bailey, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.