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Enabling immersion lithography and double patterning
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Impact of patterning strategy on mask fabrication beyond 32 nm
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S. Mimotogi, T. Higaki, H. Kanai, S. Tanaka, M. Satake, Y. Kitamura, K. Kodera, K. Ishigo, T. Kono, M. Asano, K. Takahata, S. Inoue, Impact of Patterning Strategy on Mask Fabrication Beyond 32 nm, Proc. of SPIE 7028, 702814 (2008).
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Double patterning requirements for optical lithography and prospects for optical extension without double patterning
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A. Hazelton, S. Wakamoto, S. Hirukawa, M. McCallum, N. Migóme, J. Ishikawa, C. Lapeyre, I. Guilmeau, S. Barnola, S. Gaugiran, Double patterning requirements for optical lithography and prospects for optical extension without double patterning, Proc. of SPIE 6924, 69240R (2008).
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Challenges of 29 nm half-pitch NAND FLASH STI patterning with 193nm dry lithography and self-aligned double patterning
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M. C. Chiu, B. S.-M. Lin, M. F. Tsai, Y. S. Chang, M. H. Yeh, T. H. Ying, C. Ngai, J. Jin, S. Yuen, S. Huang, Y. Chen, L. Miao, K. Tai, A. Conley, I. Liu, Challenges of 29 nm Half-Pitch NAND FLASH STI Patterning with 193nm Dry Lithography and self-aligned double patterning, Proc. of SPIE 7140, 714021 (2008).
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Using scatterometry to improve process control during the spacer pitch-splitting process
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S. Corboy, C. MacNaughton, T. Gubiotti, M. Wollenweber, Using Scatterometry to improve process control during the spacer pitch-splitting process, Proc. of SPIE 7140, 714025 (2008).
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Issues and challenges of double patterning lithography in DRAM
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S.-M. Kim, S.-Y. Koo, J.-S. Choi, Y.-S. Hwang, J.-W. Park, E.-K. Kang, C-M. Lim, S.-C. Moon, J.-W. Kim, Issues and challenges of Double Patterning Lithography in DRAM, Proc. of SPIE 6520, 65200H (2007).
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Manufacturability issues with double patterning for 50 nm Half-pitch single damascene applications, using RELACS Shrink and corresponding OPC
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M. O. Beeck, J. Versluijs, V. Wiaux, T. Vanderweyer, I. Ciofi, H. Struyf, D. Hendrckx, J. V. Olmen, Manufacturability issues with double patterning for 50 nm Half-pitch single damascene applications, using RELACS Shrink and corresponding OPC, Proc. of SPIE 6520, 652001 (2007).
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Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool
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Ultra-low kl oxide contact hole formation and metal filling using resist contact hole pattern by double L&S formation method
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Double patterning with multilayer hard mask shrinkage for sub-.25kl lithography
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H. J. Liu, W. H. Hsieh, C. H. Yeh, J. S. Wu, H. W. Chan, W. B. Wu, F. Y. Chen, T. Y. Huang, C. L. Shin, J. P. Lin, Double patterning with multilayer hard mask shrinkage for sub-.25kl lithography, Proc. of SPIE 6520, 65202J (2007).
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Litho-Only double patterning approaches: Positive-negative versus positive-positive tone
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M. Crouse, R. Uchida, Y. van Dommelen, A. Tomoyuki, E. Schmitt-Weaver, M. Takeshita, S. Wu, R. Routh, Litho-Only double patterning approaches: positive-negative versus positive-positive tone, J. Micro/Nanolith. MEMS MOEMS 8, 011006 (2009).
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Full-chip pitch/pattern splitting for lithography and spacer double patterning techniques
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T-B Chiou, R. Socha, H-Y Kang, A. C Chen, S. Hsu, Full-chip pitch/pattern splitting for lithography and spacer double patterning techniques, Proc. SPIE 71401Z (2008).
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