Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2011, Pages 125-130

  Matsumoto, Keiji ^a   Ibaraki, Soichiro ^a   Sueoka, Kuniaki ^a   Sakuma, Katsuyuki ^a   Kikuchi, Hidekazu ^a   Orii, Yasumitsu ^a   Yamada, Fumiaki ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

equivalent thermal conductivity; interconnections; thermal resistance; Three dimensional (3D) chip stack

Indexed keywords

COOLING SOLUTIONS; DESIGN PHASE; DIFFUSED RESISTORS; EQUIVALENT THERMAL CONDUCTIVITY; INTERCONNECTIONS; PN JUNCTION DIODES; SI CHIPS; STACKED STRUCTURE; STEADY-STATE THERMAL RESISTANCE; TEST CHIPS; THERMAL RESISTANCE; THREE-DIMENSIONAL (3D); THREE-DIMENSIONAL (3D) CHIP STACK;

THERMAL VARIABLES MEASUREMENT; THREE DIMENSIONAL;

THERMAL CONDUCTIVITY;

EID: 79957639703     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2011.5767189     Document Type: Conference Paper

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