Investigations of cooling solutions for three-dimensional (3D) chip stacks

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2010, Pages 25-32

  Matsumoto, Keiji ^a   Ibaraki, Soichiro ^a   Sato, Masaaki ^a   Sakuma, Katsuyuki ^a   Orii, Yasumitsu ^a   Yamada, Fumiaki ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

Chip stack; Cooling solution; Interconnections; Thermal resistance; Three dimensional (3D)

Indexed keywords

CIRCUIT DENSITY; COOLING METHODS; COOLING PERFORMANCE; COOLING SOLUTIONS; LEAD-FREE; MICROCHANNEL COOLERS; PERFORMANCE ENHANCEMENTS; THERMAL RESISTANCE; THREE-DIMENSIONAL (3D);

THERMAL VARIABLES MEASUREMENT; THREE DIMENSIONAL;

COOLING;

EID: 77952626661     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2010.5444319     Document Type: Conference Paper

References (12)

1. M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future System-on-Silicon LSI chips," IEEE MICRO, Vol 18, no. 4, pp.17-22, Jul/Aug. (1998)
2. P. Ramm, A. Klumpp, R. Merkel, J. Weber, R. Wieland, A. Ostmann, and J. Wolf, "3D System Integration Technologies," Materials Research Society Symposium Proceedings, Boston, (2003)
3. K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E.J. Sprogis, S.K. Kang, R.J. Polastre, R.R. Horton, and J. U. Knickerbocker, "3D Chip-Stacking Technology with Through-Silicon Vias and Low-Volume Lead-Free Interconnections," IBM J. Res. & Dev. 52, No. 6, 611-622, (2008)
4. C.R.King, D.Sekar, M.S.Bakir, B.Dang, J.Pikarsky, J.D. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," Electronic Components and Technology Conference (ECTC ), p.1, 2008
5. T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann and H. Reichl, "Interlayer Cooling Potential in Vertically Integrated Packages," Microsystem Technol. p.57, Vol.15(1), 2009
6. K. Matsumoto; Y. Taira, "Thermal resistance measurements of interconnections, for the Investigation of the thermal resistance of a three-dimensional (3D) chip stack",Semiconductor Thermal Measurement and Management Symposium (Semi-Therm), p.321, 2009.
7. F. Chen, J. Gill, D. Harmon, T. Sullivan, B. Li, A. Strong, H. Rathore, D. Edelstein, C-C, Yang, A. Cowley, and L. Clevenger, "Measurements of effective thermal conductivity for advanced interconnect structures with varuous composite low-k dielectrics", International Reliability Physics Symposium, 2004.
8. K. Matsumoto; K. Sakuma; F. Yamada; Y. Taira, "Investigation of the thermal resistance of a three-dimensional (3D) chip stack from the thermal resistance measurement and modeling of a single-stacked-chip" , Internatinal Conference on Electronics Packaging, p.478, 2008.
9. K. Matsumoto; Y. Taira, "Thermal characterization of a three-dimensional (3D) chip stack" , Internatinal Conference on Electronics Packaging (ICEP), p., 2009.
10. R.J.Fields, S.R.Low Third, and G.K.Lucey, Jr., "Physical and mechanical properties of intermetallic compounds commonly found in solder joints", Published in Metal Science of Joining, Proceedings of TMS Symposium, 1991.
11. Y. Terada; K. Ohkubo; T. Mohri; T. Suzuki, "Thermal conductivity of intermetallic compounds with metallic bonds," Materials Transactions, vol.43, p.3167, 2002.
12. P. Jacobsson; B. Sundqvist, "Pressure dependence of the thermal and electrical conductivities of the intermetallic compounds AnCu ans AuCu3," J. Phys. Chem. Solids, vol.49, p.441, 1998.