Die-to-wafer 3D integration technology for high yield and throughput

Materials Research Society Symposium Proceedings

Volumn 1112, Issue , 2009, Pages 201-210

  Sakuma, Katsuyuki ^a   Andry, Paul S ^b   Tsang, Cornelia K ^b   Oyama, Yukifumi ^c   Patel, Chirag S ^b   Sueoka, Kuniaki ^a   Sprogis, Edmund J ^d   Knickerbocker, John U ^b  

^a IBM RESEARCH TOKYO   (Japan)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM JAPAN LTD   (Japan)

^d IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; DIE CAVITY; HIGH YIELD; KEY PROCESS; LEAD FREE SOLDERS; PROCESS COMPLEXITY; ROADMAP; SCALING PROBLEM; TEST VEHICLE; THERMAL RELIABILITY; THREE-DIMENSIONAL (3D); THROUGH SILICON VIAS;

AUTOMOBILE PARTS AND EQUIPMENT; DIES; INTEGRATION; LEAD; SILICON WAFERS; TECHNOLOGICAL FORECASTING; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 70449565332     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. T. C. Chen, "Where Si-CMOS Is Going: Trendy Hype vs Real Technology," presented at the IEEE ISSCC, San Francisco, CA, 2006.
2. W. Haensch, "Why Should We Do 3D Integration?," Design Aulomalion Conference (DAC), 2008, pp. 674-675
3. S. Borkar, "Thousand Core Chips-A Technology Perspective," Design Aulomalion Conference (DAC), 2007, pp. 746-749
4. J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, M.J. Interrante, C.S. patel, R.J. Polastre, K. Sakuma, R. Sirdeshmukh, E.J. Sprogis, S.M. Sri-Jayantha, A.M. Stephens, A.W. Topol, C.K. Tsang, B.C. Webb, and S.L. Wright, IBM J. Res. & Dev. 52, No. 6, 553-569
5. K. Sakuma, P. S. Andry, C. K. Tsang, K. Sueoka, Y. Oyama, C. Patel, B. Dang, S.L. Wright, B.C. Webb, E. Sprogis, R. Polastre, R. Horton, and J.U. Knickerbocker, "Characterization of Stacked Die Using Die-to-Wafer Integration for High Yield and Throughput," proceedings of the Electronic Components and Technology Conference (ECTC), May 27-30, 2008.
6. S. J. Koester, A. M. Young, R. R. Yu, S. Purushothaman, K.-N. Chen, D. C. La Tulipe Jr., N. Rana, L. Shi, M. R. Wordeman, and E. J. Sprogis, "Wafer-level 3D integration technology," IBM J. Res. & Dev. 52, No. 6, 583-597
7. M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future System-on-Silicon LSI chips," IEEE MICRO, Vol. 18, no. 4, pp. 17-22, Jul/Aug. (1998)
8. P. Ramm, A. Klumpp, R. Merkel, J. Weber, R. Wieland, A. Ostmann, and J. Wolf, "3D System Integration Technologies," Materials Research Society Symposium Proceedings, Boston, (2003)
9. A.W. Topol, D.C. La Tulipe, L. Shi, S.M. Alam, D.J. Frank, S.E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D. DiMilia, M.T. Robson, E. Duch, M. Farinelli, C. Wang, R.A. Conti, D.M. Canaperi, L. Deligianni, A. Kumar, K.T. Kwietniak, C. D'Emic, J. Ott, A.M. Young, K.W. Guarini and M. Ieong, "Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)," Proceedings of the Electron Devices Meeting, 5-7 Dec. 2005 Page(s):352-355
10. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabuncuoglu Tezcan, Z. Tokei, J. Vaes, J. Van Aelst and E. Beyne, "3D Integration by Cu-Cu Thermo-compression Bonding of Extremely Thinned Bulk-Si Die Containing 10μm Pitch Through-Si Vias," Proceedings of the International Electron Devices Meeting, San Francisco, CA, 2006, pp. 1-4.
11. K.-N. Chen, S. H. Lee, P. S. Andry, C. K. Tsang, A. W. Topol, Y.-M. Lin, J.-Q. Lu, A. M. Young, M. leong, and W. Haensch, "Structure, Design and Process Control for Cu Bonded Interconnects in 3D Integrated Circuits," Proceedings of the International Electron Devices Meeting, San Francisco, CA, 2006, pp. 1-4.
12. P. Morrow, M. J. Kobrinsky, S. Ramanathan, C.-M. Partk, M. Harmes, V. Ramachandrarao, H.-M. Park, G. Kloster, S. List, and S. Kim, "Wafer-Level 3D Interconnects Via Cu Bonding," Proceedings of the UC Berkeley Extension Advanced Metallization Conference, Berkeley, CA, pp. 125-130 (2004).
13. K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E.J. Sprogis, S.K. Kang, R.J. Polastre, R.R. Horton, and J. U. Knickerbocker, "3D Chip-Stacking Technology with Through-Silicon Vias and Low-Volume Lead-Free Interconnections," IBM J. Res. & Dev. 52, No. 6, 611-622
14. B. Dang, S.L. Wright, P.S. Andry, E.J. Sprogis, C.K. Tsang, M.J. Interrante, B.C. Webb, R.J. Polastre, R.R. Horton, C.S. Patel, A. Sharma, J. Zheng, K. Sakuma, and J. U. Knickerbocker, "3D chip stacking with C4 technology," IBM J. Res. & Dev. 52, No. 6, 599-609
15. P. S. Andry, C. K. Tsang, B. C. Webb, E. J. Sprogis, S. L. Wright, B. Dang, and D. G. Manzer, "Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications," IBM J. Res. & Dev. 52, No. 6, 571-581
16. C.K. Tsang, P.S. Andry, E.J. Sprogis, C.S. Patel, B.C. Webb, D.G. Manzer, and J.U. Knickerbocker, "CMOS-Compatible Silicon Through-vias for 3D Process Integration," Materials Research Society Symposium Proceedings, Boston, MA, (2006)
17. JEDEC Solid State Technology Association, Electronic Industry Association; see http://wvvw.iedcc.org/Home/about-jedec.cfm.