Fabrication of Si single-electron transistors having double SiO2 barriers

Applied Physics Letters

Volumn 80, Issue 24, 2002, Pages 4617-4619

  Ito, Yuhei ^a   Hatano, Tsuyoshi ^a   Nakajima, Anri ^a   Yokoyama, Shin ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES; COULOMB BLOCKADE EFFECTS; DOT SIZE; ELECTRICAL CHARACTERISTIC; FABRICATION METHOD; FABRICATION PROCESS; GATE VOLTAGES; POLY-SI GRAINS; POLYCRYSTALLINE-SI; SELF ALIGNMENT; SELF-ALIGNED; SINGLE ELECTRON; SOURCE AND DRAINS;

DRAIN CURRENT; FABRICATION; MOS DEVICES; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON COMPOUNDS; SINGLE ELECTRON TRANSISTORS; TRANSIENTS; TRANSISTORS;

SEMICONDUCTING SILICON;

EID: 79956057155     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1485306     Document Type: Article

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