Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 1898-1901

  Xu, Wei ^a   Zhang, Tong ^a   Chen, Yiran ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b SEAGATE TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAMS; CELLS; CIRCUIT SIMULATION; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; DIGITAL STORAGE; LOGIC GATES; MAGNETIC DEVICES; NETWORKS (CIRCUITS); TECHNICAL PRESENTATIONS;

CELL STRUCTURING; CONTENT-ADDRESSABLE MEMORY; NOISE MARGIN;

CYTOLOGY;

EID: 51749091956     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541813     Document Type: Conference Paper

References (6)

1. M. Hosomi et al., "A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM," in IEEE International Electron Devices Meeting (IEDM), 2005, pp. 459-462.
2. Z. Diao et al., "Spin-transfer torque switching in magnetic tunnel junction and spin-tansfer torque random access memory," Journal of Physics: Condensed Matter, vol. 19, 165209, April 2007.
3. T. Kawahara et al., "2Mb spin-transfer torque ram (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read," in Proc. of 2007 IEEE International Solid-State Circuits Conference, Feb. 2007, pp. 480-481.
4. K. Pagiamtzis, "Content-addressable memory (CAM) circuits and architectures: A tutorial and survey," IEEE Journal of Solid State Circuits, vol. 41, pp. 712-727, Mar. 2006.
5. R. Scheuerlein et al., "A 10 ns read and write nonvolatile memory array using a magnetic tunnel junction and fet switch in each cell," in Proc. of 2000 Symposium on VLSI Circuits Digest of Technical Papers, Feb. 2000, pp. 128-129.
6. M. Aoki, H. Iwasa, and Y. Sato, "A novel voltage sensing 1T/2MTJ cell with resistance ratio for highly stable and scalable MRAM," in Proc. of 2005 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2005, pp. 170-171.