Fine-grained supply gating through hypergraph partitioning and Shannon decomposition for active power reduction

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 373-378

  Leinweber, Lawrence ^a   Bhunia, Swarup ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

Active power; Hypergraph partitioning; Low power design; Supply gating

Indexed keywords

BENCHMARKING; CHLORINE COMPOUNDS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; CONSERVATION; ELECTRIC CONVERTERS; ENERGY CONSERVATION; ENERGY EFFICIENCY; INDUSTRIAL ENGINEERING; LOGIC DESIGN; NANOTECHNOLOGY; NETWORKS (CIRCUITS); STANDBY POWER SYSTEMS; SWITCHING CIRCUITS; SWITCHING THEORY; TECHNOLOGY; TESTING;

65NM TECHNOLOGY; ACTIVE LEAKAGE; ACTIVE MODE; ACTIVE POWER; ADDRESS POWER; ARCHITECTURAL LEVELS; BATTERY LIFE; CAD TOOLS; COMBINATIONAL LOGICS; COMPLEX CIRCUITS; DESIGN METHODOLOGIES; DESIGN OBJECTIVES; DIE AREA; DYNAMIC POWER REDUCTION; ENERGY-EFFICIENT; HIGH-PERFORMANCE LOGIC; HYPERGRAPH PARTITIONING; LEAKAGE POWER; LOW POWER DESIGN; PORTABLE DEVICES; POWER CONSUMPTION; POWER REDUCTIONS; SHANNON DECOMPOSITION; SIMULATION RESULTS; SMALL CLUSTERS; STANDBY POWER; SUPPLY GATING; SWITCHING POWER; TOTAL POWER;

LOGIC CIRCUITS;

EID: 49749087929     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484709     Document Type: Conference Paper

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