Ferroelectric-gate thin-film transistor fabricated by total solution deposition process

Japanese Journal of Applied Physics

Volumn 50, Issue 4 PART 2, 2011, Pages

  Miyasako, Takaaki ^a   Trinh, Bui Nguyen Quoc ^a   Onoue, Masatoshi ^a   Kaneda, Toshihiko ^a   Tue, Phan Trong ^c   Tokumitsu, Eisuke ^a,b   Shimoda, Tatsuya ^a,c  

^a JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^c JAPAN ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL SOLUTION DEPOSITION; CRYSTALLINE QUALITY; CURRENT SATURATION; EPITAXIALLY GROWN; GATE ELECTRODES; GATE INSULATOR; HETEROSTRUCTURES; INDIUM TIN OXIDE; INTERFACIAL LAYER; MEMORY WINDOW; N-CHANNEL TRANSISTORS; ON/OFF CURRENT RATIO; OUTPUT CHARACTERISTICS; PB(ZR , TI)O; PZT; SOLUTION DEPOSITION; SOURCE/DRAIN ELECTRODES; SRTIO; SUBTHRESHOLD; VACUUM PROCESS; VOLTAGE SWINGS;

DRAIN CURRENT; FABRICATION; HYSTERESIS; LEAD; PEROVSKITE; SEMICONDUCTING ORGANIC COMPOUNDS; THIN FILM TRANSISTORS; TIN; ZIRCONIUM;

FERROELECTRICITY;

EID: 79955378325     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.50.04DD09     Document Type: Article

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