Nonvolatile memory operations of metal-ferroelectric-insulator-semiconductor (MFIS) FET's using PLZT/STO/Si(100) structures

IEEE Electron Device Letters

Volumn 18, Issue 4, 1997, Pages 160-162

  Tokumitsu, Eisuke ^a,b   Nakamura, Ryo Ichi ^b   Ishiwara, Hiroshi ^a,b  

^a IEEE   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENT CONTROL; FERROELECTRIC MATERIALS; HYSTERESIS; NONVOLATILE STORAGE; PERMITTIVITY; SEMICONDUCTOR DEVICE STRUCTURES; STRONTIUM COMPOUNDS;

BUFFER LAYER; FERROELECTRIC FILM;

MISFET DEVICES;

EID: 0031124778     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.563315     Document Type: Article

References (8)

1. J. L. Moll and Y. Tarui, "A new solid state resistor," IEEE Trans. Electron Devices, vol. ED-10, p. 338, 1963.
2. H. Ishiwara, "Proposal of adaptive-learning neuron circuits with ferroelectric nanalog-memory weights," Jpn. J. Appl. Phys., vol. 32, no. 1B, pp. 442-446, 1993
3. 3 films with Si substrate," Jpn. J. Appl. Phys., vol. 33, no. 9B, pp. 5172-5177, 1994.
4. 3 buffer layers," in Proc. Mater. Res. Soc. Symp., 1995, vol. 361, pp. 427-432.
5. Y. Nakao, T. Nakamura, A. Kamisawa, and H. Takasu, "Study on ferroelectric thin films for application to NDRO nonvolatile memories," Inter. Ferroelect., vol. 6, pp. 23-34, 1995.
6. 3-covered Si substrates," Jpn. J. Appl. Phys., vol. 34, no. 9B, pp. 5202-5206, 1995.
7. J. Fukushima, K. Kodaira, and T. Matsushita, "Preparation of ferroelectric PZT films by thermal decomposition of organometallic compounds," J. Mater. Sci., vol. 19 pp. 595-598, 1984.
8. E. Tokumitsu, R. Nakamura, and H, Ishiwara, "Fabrications of ferroelectric-gate field effect transistors using P(L)ZT films," J. Korean Phys. Soc., to be published.