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Volumn 47, Issue 3, 2011, Pages 624-628

Floating-gate coupling canceller for multi-level cell NAND flash

Author keywords

Coupling noise; floating gate coupling canceller (FG CC); multi level cell (MLC) NAND flash memory

Indexed keywords

MEMORY ARCHITECTURE; NAND CIRCUITS;

EID: 79952136198     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2010.2101054     Document Type: Article
Times cited : (25)

References (20)
  • 1
    • 0032304222 scopus 로고    scopus 로고
    • Nonvolatile multilevel memories for digital applications
    • Dec.
    • B. Ricco et al., "Nonvolatile multilevel memories for digital applications," Proc. IEEE, vol. 86, no. 12, pp. 2399-2423, Dec. 1998.
    • (1998) Proc. IEEE , vol.86 , Issue.12 , pp. 2399-2423
    • Ricco, B.1
  • 3
    • 0242551720 scopus 로고    scopus 로고
    • A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications
    • Nov.
    • J. Lee et al., "A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1934-1942, Nov. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.11 , pp. 1934-1942
    • Lee, J.1
  • 4
    • 0000027444 scopus 로고    scopus 로고
    • A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming
    • May
    • H. Nobukata et al., "A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 682-690, May 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.5 , pp. 682-690
    • Nobukata, H.1
  • 5
    • 0032140032 scopus 로고    scopus 로고
    • A multipage cell architecture for high-speed programming multilevel NAND flash memories
    • Aug.
    • K. Takeuchi, T. Tanaka, and T. Tanzawa, "A multipage cell architecture for high-speed programming multilevel NAND flash memories," IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1228-1238, Aug. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.8 , pp. 1228-1238
    • Takeuchi, K.1    Tanaka, T.2    Tanzawa, T.3
  • 6
    • 3142694456 scopus 로고    scopus 로고
    • Program schemes for multilevel flash memories
    • DOI 10.1109/JPROC.2003.811714
    • M. Grossi, M. Lanzoni, and B. Ricco, "Program schemes for multilevel flash memories," Proc. IEEE, vol. 91, no. 4, pp. 594-601, Apr. 2003. (Pubitemid 43773312)
    • (2003) Proceedings of the IEEE , vol.91 , Issue.4 , pp. 594-601
    • Grossi, M.1    Lanzoni, M.2    Ricco, B.3
  • 8
    • 50249139679 scopus 로고    scopus 로고
    • Program disturb phenomenon by DIBL in MLC NAND flash device
    • May
    • D. Oh, "Program disturb phenomenon by DIBL in MLC NAND flash device," in Proc. Joint NVSMV/ICMTD 2008, May 2008, pp. 5-7.
    • (2008) Proc. Joint NVSMV/ICMTD 2008 , pp. 5-7
    • Oh, D.1
  • 9
    • 0034179167 scopus 로고    scopus 로고
    • A source-line programming scheme for low-voltage operation NAND flash memories
    • May
    • K. Takeuchi, S. Satoh, K. Imamiya, and K. Sakui, "A source-line programming scheme for low-voltage operation NAND flash memories," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 672-681, May 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.5 , pp. 672-681
    • Takeuchi, K.1    Satoh, S.2    Imamiya, K.3    Sakui, K.4
  • 10
    • 0031638358 scopus 로고    scopus 로고
    • A novel channel boost capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND flash memories
    • Jun.
    • S. Satoh et al., "A novel channel boost capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND flash memories," in Symp. VLSI Technol. Dig. Tech. Papers, Jun. 1998, pp. 108-109.
    • (1998) Symp. VLSI Technol. Dig. Tech. Papers , pp. 108-109
    • Satoh, S.1
  • 13
    • 4344701872 scopus 로고    scopus 로고
    • On-chip error correcting techniques for new-generation flash memories
    • DOI 10.1109/JPROC.2003.811709
    • S. Gregori, A. Cabrini, O. Khouri, and G. Torelli, "On-chip error correcting techniques for new-generation flash memories," Proc. IEEE, vol. 91, no. 4, pp. 602-616, April 2003. (Pubitemid 43773313)
    • (2003) Proceedings of the IEEE , vol.91 , Issue.4 , pp. 602-616
    • Gregori, S.1    Cabrini, A.2    Khouri, O.3    Torelli, G.4
  • 15
    • 34547345637 scopus 로고    scopus 로고
    • Design of on-chip error correction systems for multilevel NOR and NAND flash memories
    • DOI 10.1049/iet-cds:20060275
    • F. Sun, S. Devarajan, K. Rose, and T. Zhang, "Design of on-chip error correction systems for multilevel NOR and NAND flash memories," IET. Circuits, Devices & Systems, vol. 1, no. 3, pp. 241-249, 2007. (Pubitemid 47152752)
    • (2007) IET Circuits, Devices and Systems , vol.1 , Issue.3 , pp. 241-249
    • Sun, F.1    Devarajan, S.2    Rose, K.3    Zhang, T.4
  • 16
    • 0029404872 scopus 로고
    • A 3.3 v 32 Mb NAND flash memory with incremental step pulse programming scheme
    • Nov.
    • K. Suh et al., "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.11 , pp. 1149-1156
    • Suh, K.1
  • 17
    • 3142773890 scopus 로고    scopus 로고
    • Introduction to flash memory
    • Apr.
    • R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.
    • (2003) Proc. IEEE , vol.91 , Issue.4 , pp. 489-502
    • Bez, R.1    Camerlenghi, E.2    Modelli, A.3    Visconti, A.4
  • 18
    • 0027816546 scopus 로고
    • A hig capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories
    • Y. Hisamune et al., "A hig capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories," in IEDM Tech. Dig., 1993, pp. 19-22.
    • (1993) IEDM Tech. Dig. , pp. 19-22
    • Hisamune, Y.1
  • 19
    • 0036575326 scopus 로고    scopus 로고
    • Effects of floating-gate interference on NAND flash memory cell operation
    • DOI 10.1109/55.998871, PII S0741310602040405
    • J. Lee, S. Hur, and J. Choi, "Effects of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Lett., vol. 23, no. 5, pp. 264-266, May 2002. (Pubitemid 34630852)
    • (2002) IEEE Electron Device Letters , vol.23 , Issue.5 , pp. 264-266
    • Lee, J.-D.1    Hur, S.-H.2    Choi, J.-D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.